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authorStefan Pintilie <stefanp@ca.ibm.com>2024-07-29 11:17:04 -0400
committerGitHub <noreply@github.com>2024-07-29 11:17:04 -0400
commit53c37f300dd1b450671f2aee4cc649c380adb5ad (patch)
treeaf3dfd2a421eb02a6cb7bad2462caf514d786ac3 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
parent363c1e6e517281ad387fd91787545d632e7c48b6 (diff)
[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)
On PowerPC there are 128 bit VSX registers. These registers are half overlapped with 64 bit floating point registers (FPR). The 64 bit half of the VXS register that does not overlap with the FPR does not overlap with any other register class. The FPR are the only subregisters of the VSX registers but they do not fully cover the 128 bit super register. This leads to incorrect lane masks being created. This patch adds phony registers for the other half of the VSX registers in order to fully cover them and to make sure that the lane masks are not the same for the VSX and the floating point register.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
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