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| author | Salvatore Dipietro <dipiets@amazon.com> | 2022-12-09 10:36:16 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2022-12-09 10:36:16 +0000 |
| commit | 3a894fd90b0569b4ddd9782e3ab3a4b1e85c0075 (patch) | |
| tree | d476137a5b6cfb94237e5ba92768a4d49364ccda /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 195af8e034f08de9b620fb434a4e816c74575e86 (diff) | |
[AArch64] Lower READCYCLECOUNTER using MRS CNTVCT_EL0
As suggested in D12425 it would be better for the readcyclecounter
function on ARM architecture to use the CNTVCT_EL0 register
(Counter-timer Virtual Count register) instead of the PMCCNTR_EL0
(Performance Monitors Cycle Count Register) because the PMCCNTR_EL0 is a
PMU register which, depending on the configuration, it might always
return zeroes and it doesn't guaranteed to always be increased.
Differential Revision: https://reviews.llvm.org/D136999
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions