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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-05-30 19:50:55 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-06-15 11:33:16 -0400 |
| commit | 2ca552322c29b61e8c20a0b31cf452de88d8af1c (patch) | |
| tree | 68b9850b326eaa0af4f2aea7464a7fca12d01083 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | d9e0bbd17b0e61e9f59e6f80c748f7893f7e8d9c (diff) | |
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
These are legal since we can do a 96-bit load on some subtargets, but
this is only for vector loads. If we can't widen the load, it needs to
be broken down once known scalar. For 16-byte alignment, widen to a
128-bit load.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions