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| author | Craig Topper <craig.topper@sifive.com> | 2022-01-07 19:50:44 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-01-07 20:02:10 -0800 |
| commit | 042394b69e99c8e9e502209af1c5ff529ac30586 (patch) | |
| tree | 7b3ea112fd6c80f0e8ad53d937c278d3977c0467 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 4e2ec7e38dc2c4604d527d29ecbc8ac0387b06f0 (diff) | |
[RISCV] Add a command line option to control the LMUL used by TTI's getRegisterBitWidth.
By default we return the width of an LMUL=1 register. We can enable
testing with larger LMUL values by returning a larger bit width.
This patch adds a RISCV specific option to provide a LMUL which will be
multiplied by the LMUL=1 bit width.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D116339
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions