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| author | Craig Topper <craig.topper@sifive.com> | 2022-01-18 10:29:37 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-01-18 10:36:03 -0800 |
| commit | e32838573929ac85fc4df3058593798d10ce4cd2 (patch) | |
| tree | 34f4c1e2b527da40be33c08aa4efda800c4d54a1 /lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp | |
| parent | 755dc07d69ed5c3a4a5ef6a2de68aa10378891a0 (diff) | |
Revert "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."
This reverts commit b634f8a663d56877663f5224a785d9f0263c4176.
I broke the SimplifyDemandedBits code, but we don't have tests.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp')
0 files changed, 0 insertions, 0 deletions