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| author | Craig Topper <craig.topper@sifive.com> | 2022-01-18 10:42:47 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-01-18 10:52:43 -0800 |
| commit | b3a0ec7645dbd2978bd43f372933d1d1cd36f132 (patch) | |
| tree | b663938446623afd0eef4dbefd1c8e0e035b65df /lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp | |
| parent | de1600a1d946d1bd9ca5f7b0711012a8f31a66e2 (diff) | |
[RISCV] Remove DemandedBits handling for FSR/FSL until we have test cases for it.
Testing may be easier after D117468. Right now we get demanded bits
optimizations done on ISD::FSHL/FSHR before they become FSR/FSL. This
makes it hard to test.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp')
0 files changed, 0 insertions, 0 deletions