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| author | Georgiy Samoylov <g.samoylov@syntacore.com> | 2025-11-11 18:39:09 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-11-11 15:39:09 +0000 |
| commit | 80e7fe898cc4e64c38882183568276fa11b183b1 (patch) | |
| tree | b605e452060caa1729f3e1415d07c1f4b4b542cd /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h | |
| parent | eb614cda37bdf14d5371f6b41a475c68c9a7fdec (diff) | |
[lldb][RISCV] Fix float load and stores in RISC-V emulator (#167490)
This patch fixes 2 fundamental problems in emulating `FLW`, `FSW`, `FLD`
and `FSD` instructions.
1. Instructions immediate wasn't sign extended
2. Store instructions always wrote for 64 bits to memory
Also this patch fixes 2 lldb tests for RISC-V: TestThreadJump.py and
TestBreakpointHitCount.py
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h')
0 files changed, 0 insertions, 0 deletions