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| author | Stefan Pintilie <stefanp@ca.ibm.com> | 2024-07-23 21:59:27 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-23 21:59:27 -0400 |
| commit | 26fa399012da00fbf806f50ad72a3b5f0ee63eab (patch) | |
| tree | 0461996970e2f76119162d459eeda93dea500fe1 /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp | |
| parent | 4f79ef4efff432a93005b156726587c8c5a5ac17 (diff) | |
[RegisterCoalescer] Fix SUBREG_TO_REG handling in the RegisterCoalescer. (#96839)
The issue with the handling of the SUBREG_TO_REG is that we don't join
the subranges correctly when we join live ranges across the
SUBREG_TO_REG. For example when joining across this:
```
32B %2:gr64_nosp = SUBREG_TO_REG 0, %0:gr32, %subreg.sub_32bit
```
we want to join these live ranges:
```
%0 [16r,32r:0) 0@16r weight:0.000000e+00
%2 [32r,112r:0) 0@32r weight:0.000000e+00
```
Before the fix the range for the resulting merged `%2` is:
```
%2 [16r,112r:0) 0@16r weight:0.000000e+00
```
After the fix it is now this:
```
%2 [16r,112r:0) 0@16r L000000000000000F [16r,112r:0) 0@16r weight:0.000000e+00
```
Two tests are added to this fix. The X86 test fails without the patch.
The PowerPC test passes with and without the patch but is added as a way
track future possible failures when register classes are changed in a
future patch.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp')
0 files changed, 0 insertions, 0 deletions
