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| author | Craig Topper <craig.topper@sifive.com> | 2024-08-16 14:54:51 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-16 14:54:51 -0700 |
| commit | ebe7265b142f370f0a563fece5db22f57383ba2d (patch) | |
| tree | c56f5d49056edb8bb9b6673d542cb7ae92abb104 /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface | |
| parent | bd9f2c2ba095fa8345bba9f74b279ff20d5ddaab (diff) | |
[Mips] Fix fast isel for i16 bswap. (#103398)
We need to mask the SRL result to 8 bits before ORing in the SLL. This
is needed in case bits 23:16 of the input aren't zero. They will have
been shifted into bits 15:8.
We don't need to AND the result with 0xffff. It's ok if the upper 16
bits of the register are garbage.
Fixes #103035.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface')
0 files changed, 0 insertions, 0 deletions