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authorHimadhith <79003240+Himadhith@users.noreply.github.com>2025-11-21 12:26:58 +0530
committerGitHub <noreply@github.com>2025-11-21 12:26:58 +0530
commite4a4bb0f6d3b3b9f3ccba79202a9074415b7dd71 (patch)
tree8f0b382089a107f4247888f7c4d98b553c501e60 /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface/ScriptedProcessPythonInterface.h
parentcc5185bd146bed96d0d9e23263a56b6965d8572f (diff)
[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1} (#160882)
This patch optimizes vector addition operations involving **`all-ones`** vectors by leveraging the generation of vectors of -1s(using `xxleqv`, which is cheaper than generating vectors of 1s(`vspltisw`). These are the respective vector types. `v2i64`: **`A + vector {1, 1}`** `v4i32`: **`A + vector {1, 1, 1, 1}`** `v8i16`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1}`** `v16i8`: **`A + vector {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}`** The optimized version replaces `vspltisw (4 cycles)` with `xxleqv (2 cycles)` using the following identity: `A - (-1) = A + 1`. --------- Co-authored-by: himadhith <himadhith.v@ibm.com> Co-authored-by: Tony Varghese <tonypalampalliyil@gmail.com>
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