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| author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2024-08-19 11:50:32 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-19 11:50:32 +0800 |
| commit | a80a90e34b1f26422ebf56e922abe2c193607c81 (patch) | |
| tree | e0fbcdc8c8caa646e662d82feda4fd04a96f78ad /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface/ScriptedProcessPythonInterface.h | |
| parent | 731ae694a3d8f4d39e855c9a82c97d4f170fd48a (diff) | |
[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)
These two extensions add addtional instructions for carryless
multiplication with 32-bits elements and Vector-Scalar GCM
instructions.
Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface/ScriptedProcessPythonInterface.h')
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