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| author | Craig Topper <craig.topper@sifive.com> | 2023-10-20 16:34:37 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-20 16:34:37 -0700 |
| commit | 972709a74a0c47998e1caeca888673a761dae9ca (patch) | |
| tree | 7d6af04b3ba82e92fa2d4767813315347caafd1d /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.h | |
| parent | 6456e0bbbbd7c8c2783c09a426d4fb1de1d87e6e (diff) | |
[RISCV][GISel] Minor refactoring of RISCVCallReturnHandler and RISCVIncomingValueHandler to match other targets (#69757)
Forward assignValueToReg to the base class to make the copy. Add
markPhysRegUsed to contain the differences between call handling and
argument handling. Introduce RISCVFormalArgHandler.
This structure matches how AArch64, AMDGPU, and X86 are structured.
I've also added `MIRBuilder.getMRI()->addLiveIn(PhysReg);` to match the
other targets.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.h')
0 files changed, 0 insertions, 0 deletions