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| author | RolandF77 <55763885+RolandF77@users.noreply.github.com> | 2024-09-04 12:55:27 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-04 12:55:27 -0400 |
| commit | 26ba186bd0a22fac7d08ed566b00c03236b6b7a9 (patch) | |
| tree | 4081a55eb44f4ad7123ce6f7a86609394cbaa334 /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp | |
| parent | 32bc670609fe9c938bca5b3c0e70e6b3934b4641 (diff) | |
[PowerPC] Improve pwr7 codegen for v4i8 load (#104507)
There are no partial vector loads on pwr7 so current v4i8 codegen is an
int load then store to vector sized temp and re-load as vector. Try to
use lfiwax to load 32 bits into an FP reg and take advantage of VSX FP
and vector reg sharing to move the result to the right vector position.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp')
0 files changed, 0 insertions, 0 deletions