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| author | Anton Sidorenko <anton.sidorenko@syntacore.com> | 2024-08-14 11:42:31 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-14 11:42:31 +0300 |
| commit | 5ab99bf1a757c5ad7115280f374d9af4f1b98bc9 (patch) | |
| tree | 5499b12f4a51a1a7c1c3353eb64826b9b8333e1a /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface | |
| parent | 13008aa45d406a65ee7adfc7672a038e4def1ad3 (diff) | |
[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)
Syntacore SCR4 is a microcontroller-class processor core that has much
in common with SCR3, but also supports F and D extensions.
Overview: https://syntacore.com/products/scr4
Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V
processor core which scheduling model almost match SCR4.
Overview: https://syntacore.com/products/scr5
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev@syntacore.com>
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface')
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