[RISCV] Add unit strided load/store to whole register peephole (#100116)

This adds a new vector peephole that converts unmasked, VLMAX
vleN.v/vseN.v to their whole register equivalents.

It replaces the existing tablegen patterns on ISD::LOAD/ISD::STORE and
is a bit more general since it also catches VP loads and stores and
@llvm.riscv intrinsics.

The heavy lifting of detecting a VLMAX AVL and an all-ones mask is
already taken care of by existing peepholes.

0 files changed, 0 insertions, 0 deletions