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| author | Carl Ritson <carl.ritson@amd.com> | 2021-11-26 19:45:23 +0900 |
|---|---|---|
| committer | Carl Ritson <carl.ritson@amd.com> | 2021-11-26 21:05:58 +0900 |
| commit | 8967d044fc265acb332ab3d0169024e96b44c6ac (patch) | |
| tree | d532fe5ba089629fa983921b35c0aaf1911ee8a4 /lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp | |
| parent | 4af45f10cccbaabc87758c4dc50b94bfd31fe848 (diff) | |
[AMDGPU] Add SIMemoryLegalizer comments to clarify bit usage
Attempt to further document the intended cache policies requested
by different combinations of GLC, SLC and DLC bits.
GFX10 non-temporal stores are updated to set GLC.
Reviewed By: t-tye
Differential Revision: https://reviews.llvm.org/D114351
Diffstat (limited to 'lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp')
0 files changed, 0 insertions, 0 deletions