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| author | Simon Tatham <simon.tatham@arm.com> | 2020-03-03 17:37:05 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2020-03-04 08:49:27 +0000 |
| commit | 810127f6ab5d5d7e7d6b8c3ae0b96f2027437ca8 (patch) | |
| tree | f0c2b4dddde9a9c75b88e39b0ee240ac34f98750 /lldb/source/Plugins/LanguageRuntime/RenderScript/RenderScriptRuntime/RenderScriptRuntime.cpp | |
| parent | 9284abd0040afecfd619dbcf1b244a8b533291c9 (diff) | |
[ARM,MVE] Add the `vsbciq` intrinsics.
Summary:
These are exactly parallel to the existing `vadciq` intrinsics, which
we implemented last year as part of the original MVE intrinsics
framework setup.
Just like VADC/VADCI, the MVE VSBC/VSBCI instructions deliver two
outputs, both of which the intrinsic exposes: a modified vector
register and a carry flag. So they have to be instruction-selected in
C++ rather than Tablegen. However, in this case, that's trivial: the
same C++ isel routine we already have for VADC works unchanged, and
all we have to do is to pass it a different instruction id.
Reviewers: MarkMurrayARM, dmgreen, miyuki, ostannard
Reviewed By: miyuki
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D75444
Diffstat (limited to 'lldb/source/Plugins/LanguageRuntime/RenderScript/RenderScriptRuntime/RenderScriptRuntime.cpp')
0 files changed, 0 insertions, 0 deletions