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| author | Venkata Ramanaiah Nalamothu <quic_vnalamot@quicinc.com> | 2023-06-13 20:06:08 +0530 |
|---|---|---|
| committer | Venkata Ramanaiah Nalamothu <quic_vnalamot@quicinc.com> | 2023-06-13 20:18:08 +0530 |
| commit | dbbd6276f20aa8bcf472f12a16a5a895ff797313 (patch) | |
| tree | 1dd84e8d191cf0893a92ad0e7024cac3da5b4e70 /libcxx/include/algorithm | |
| parent | 5039d364547c33ca69c5289894a09c48bc91e10b (diff) | |
[RISCV][NFC] Improve encoding/decoding tests for Zbb instructions
Currently `llvm/test/MC/RISCV/rv64zbb-valid.s` doesn't cover all
the instructions e.g. `maxu` and `llvm/test/MC/RISCV/rv32zbb-valid.s`
can have rv64 run lines, similar to what Zba instruction tests have.
This patch does the following.
- Add rv64 run lines in `llvm/test/MC/RISCV/rv32zbb-valid.s`
- Keep only rv64 specific instructions in `llvm/test/MC/RISCV/rv64zbb-valid.s`
- Move rv32 instructions, with different encodings from rv64, into
`llvm/test/MC/RISCV/rv32zbb-only-valid.s`
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D152680
Diffstat (limited to 'libcxx/include/algorithm')
0 files changed, 0 insertions, 0 deletions