diff options
| author | Victor Campos <victor.campos@arm.com> | 2025-11-06 10:45:45 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-11-06 10:45:45 +0000 |
| commit | 22b6c491d69e916d9af8221a543570535c923764 (patch) | |
| tree | e11963817b69561e40983e3ff4d13161faf57335 /libc | |
| parent | 06ec47055ad1f085e64edca3f94f34f4da053ba0 (diff) | |
[libc] Enable the FPU in Arm startup code (#166349)
This patch enables the FPU in Arm startup code, which is required to run
tests on Arm configurations with hardware floating-point support.
Diffstat (limited to 'libc')
| -rw-r--r-- | libc/startup/baremetal/arm/start.cpp | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/libc/startup/baremetal/arm/start.cpp b/libc/startup/baremetal/arm/start.cpp index c089a14f5f78..474006772202 100644 --- a/libc/startup/baremetal/arm/start.cpp +++ b/libc/startup/baremetal/arm/start.cpp @@ -131,6 +131,32 @@ namespace LIBC_NAMESPACE_DECL { __arm_wsr("CPSR_c", 0x13); // SVC #endif +#ifdef __ARM_FP +// Enable FPU +#if __ARM_ARCH_PROFILE == 'M' + // Based on + // https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/Floating-Point-Unit/Enabling-the-FPU + // Set CPACR cp10 and cp11 + auto cpacr = (volatile uint32_t *const)0xE000ED88; + *cpacr |= (0xF << 20); + __dsb(0xF); + __isb(0xF); +#elif __ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R' + // Based on + // https://developer.arm.com/documentation/dui0472/m/Compiler-Coding-Practices/Enabling-NEON-and-FPU-for-bare-metal + // Set CPACR cp10 and cp11 + uint32_t cpacr = __arm_rsr("p15:0:c1:c0:2"); + cpacr |= (0xF << 20); + __arm_wsr("p15:0:c1:c0:2", cpacr); + __isb(0xF); + // Set FPEXC.EN + uint32_t fpexc; + __asm__ __volatile__("vmrs %0, FPEXC" : "=r"(fpexc) : :); + fpexc |= (1 << 30); + __asm__ __volatile__("vmsr FPEXC, %0" : : "r"(fpexc) :); +#endif +#endif + // Perform the equivalent of scatterloading LIBC_NAMESPACE::memcpy(__data_start, __data_source, reinterpret_cast<uintptr_t>(__data_size)); |