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authorWilliam <113542065+saturn691@users.noreply.github.com>2025-05-02 12:36:00 +0100
committerGitHub <noreply@github.com>2025-05-02 13:36:00 +0200
commitda3022577e1f277999922acaef9be169c20dfd48 (patch)
tree697cbdf0dc754a821c5e6fbd44f1060b0a077cd7 /libc/src/string/memory_utils/inline_memcmp.h
parent72f5ac442da0e4af3a856d11f2c6dfd1c790998d (diff)
[libc] Add support for string/memory_utils functions for AArch64 without HW FP/SIMD (#137592)
Add conditional compilation to add support for AArch64 without vector registers and/or hardware FPUs by using the generic implementation. **Context:** A few functions were hard-coded to use vector registers/hardware FPUs. This meant that libc would not compile on architectures that did not support these features. This fix falls back on the generic implementation if a feature is not supported.
Diffstat (limited to 'libc/src/string/memory_utils/inline_memcmp.h')
-rw-r--r--libc/src/string/memory_utils/inline_memcmp.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/libc/src/string/memory_utils/inline_memcmp.h b/libc/src/string/memory_utils/inline_memcmp.h
index a2ca9afd7f79..85a614b2fb95 100644
--- a/libc/src/string/memory_utils/inline_memcmp.h
+++ b/libc/src/string/memory_utils/inline_memcmp.h
@@ -20,7 +20,7 @@
#define LIBC_SRC_STRING_MEMORY_UTILS_MEMCMP inline_memcmp_x86
#elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
#include "src/string/memory_utils/aarch64/inline_memcmp.h"
-#define LIBC_SRC_STRING_MEMORY_UTILS_MEMCMP inline_memcmp_aarch64
+#define LIBC_SRC_STRING_MEMORY_UTILS_MEMCMP inline_memcmp_aarch64_dispatch
#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
#include "src/string/memory_utils/riscv/inline_memcmp.h"
#define LIBC_SRC_STRING_MEMORY_UTILS_MEMCMP inline_memcmp_riscv