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| author | Min-Yih Hsu <min.hsu@sifive.com> | 2025-09-26 11:08:51 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-26 11:08:51 -0700 |
| commit | 24bc1a60978cf6871d3381dcf92211509f658c76 (patch) | |
| tree | ded1ed827097dc2eab5e75352a5c12aa83ef8d91 /flang-rt | |
| parent | e9185af70a4898d050899aa83aa350e570459128 (diff) | |
[RISCV] Update SiFive7's scheduling models with their optimizations on permutation instructions (#160763)
In newer SiFIve7 cores like X390, permutation instructions like
vrgather.vv operates on LMUL smaller than a single DLEN could yield a
constant cycle. For slightly larger data that fits in the constraint of
`log2(SEW/8) + log2(LMUL) <= log2(DLEN / 32)`, these instructions can
also yield cycles that are proportional to the quadratic of LMUL, rather
than being proportional to VL.
Co-authored-by: Michael Maitland <michaeltmaitland@gmail.com>
Diffstat (limited to 'flang-rt')
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