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| author | Mikołaj Piróg <mikolaj.maciej.pirog@intel.com> | 2025-11-15 15:51:06 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-11-15 15:51:06 +0100 |
| commit | 8f6c7aa2b1f80afe58e2011cb457c5cb67337274 (patch) | |
| tree | 8ff5a5bbf37bdd69aedc7d24bd38ebe025320ce5 /compiler-rt | |
| parent | 20db716418bd102c35c29b2e05c0f20b7458e559 (diff) | |
[X86] Remove vector length (256 vs 512) distinction of AVX10 (#167736)
As in title. AVX10.x doesn't distinguish between available vector
lengths.
-mattr=avx10.x-512 and defining of macros with _512 is kept for compatibility.
Bit-positions of avx10.1/2 features in compiler-rt and X86TargetParser
are synced to match those in the gcc.
Diffstat (limited to 'compiler-rt')
| -rw-r--r-- | compiler-rt/lib/builtins/cpu_model/x86.c | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c index 45b7055abf45..b4b60986022d 100644 --- a/compiler-rt/lib/builtins/cpu_model/x86.c +++ b/compiler-rt/lib/builtins/cpu_model/x86.c @@ -229,10 +229,8 @@ enum ProcessorFeatures { FEATURE_SM4, FEATURE_APXF, FEATURE_USERMSR, - FEATURE_AVX10_1_256, - FEATURE_AVX10_1_512, - FEATURE_AVX10_2_256, - FEATURE_AVX10_2_512, + FEATURE_AVX10_1 = 114, + FEATURE_AVX10_2 = 116, FEATURE_MOVRS, CPU_FEATURE_MAX }; @@ -1093,18 +1091,11 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, bool HasLeaf24 = MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX); if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1) && HasLeaf24) { - bool Has512Len = (EBX >> 18) & 1; int AVX10Ver = EBX & 0xff; - if (AVX10Ver >= 2) { - setFeature(FEATURE_AVX10_2_256); - if (Has512Len) - setFeature(FEATURE_AVX10_2_512); - } - if (AVX10Ver >= 1) { - setFeature(FEATURE_AVX10_1_256); - if (Has512Len) - setFeature(FEATURE_AVX10_1_512); - } + if (AVX10Ver >= 1) + setFeature(FEATURE_AVX10_1); + if (AVX10Ver >= 2) + setFeature(FEATURE_AVX10_2); } unsigned MaxExtLevel = 0; |