diff options
| author | Kai Luo <gluokai@gmail.com> | 2024-08-27 09:43:52 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-27 09:43:52 +0800 |
| commit | 8e901c255df45e38cb1d69a576804029e20868bf (patch) | |
| tree | 2d8edd10739129b52f2bf856af8280b08c3c3625 | |
| parent | b412ec5d3924c7570c2c96106f95a92403a4e09b (diff) | |
[PowerPC] Retire PPCExpandISel pass (#84289)
We can decide whether to expand isel or not in instruction selection
pass and early-if-conversion pass. The transformation implemented in
PPCExpandISel can be retired considering PPC backend doesn't generate
`isel` instructions post-RA.
Also if we are seeking performant branch-or-isel decision, we can turn
to selectoptimize pass.
---------
Co-authored-by: Kai Luo <lkail@cn.ibm.com>
33 files changed, 1143 insertions, 1655 deletions
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt index d866ef6b88a1..cd4c76013d20 100644 --- a/llvm/lib/Target/PowerPC/CMakeLists.txt +++ b/llvm/lib/Target/PowerPC/CMakeLists.txt @@ -54,7 +54,6 @@ add_llvm_target(PowerPCCodeGen PPCReduceCRLogicals.cpp PPCVSXFMAMutate.cpp PPCVSXSwapRemoval.cpp - PPCExpandISEL.cpp PPCPreEmitPeephole.cpp PPCLowerMASSVEntries.cpp PPCGenScalarMASSEntries.cpp diff --git a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp b/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp deleted file mode 100644 index 4c74e82cf041..000000000000 --- a/llvm/lib/Target/PowerPC/PPCExpandISEL.cpp +++ /dev/null @@ -1,491 +0,0 @@ -//===------------- PPCExpandISEL.cpp - Expand ISEL instruction ------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// A pass that expands the ISEL instruction into an if-then-else sequence. -// This pass must be run post-RA since all operands must be physical registers. -// -//===----------------------------------------------------------------------===// - -#include "PPC.h" -#include "PPCInstrInfo.h" -#include "PPCSubtarget.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/CodeGen/LivePhysRegs.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -#define DEBUG_TYPE "ppc-expand-isel" - -STATISTIC(NumExpanded, "Number of ISEL instructions expanded"); -STATISTIC(NumRemoved, "Number of ISEL instructions removed"); -STATISTIC(NumFolded, "Number of ISEL instructions folded"); - -// If -ppc-gen-isel=false is set, we will disable generating the ISEL -// instruction on all PPC targets. Otherwise, if the user set option -// -misel or the platform supports ISEL by default, still generate the -// ISEL instruction, else expand it. -static cl::opt<bool> - GenerateISEL("ppc-gen-isel", - cl::desc("Enable generating the ISEL instruction."), - cl::init(true), cl::Hidden); - -namespace { -class PPCExpandISEL : public MachineFunctionPass { - DebugLoc dl; - MachineFunction *MF; - const TargetInstrInfo *TII; - bool IsTrueBlockRequired; - bool IsFalseBlockRequired; - MachineBasicBlock *TrueBlock; - MachineBasicBlock *FalseBlock; - MachineBasicBlock *NewSuccessor; - MachineBasicBlock::iterator TrueBlockI; - MachineBasicBlock::iterator FalseBlockI; - - typedef SmallVector<MachineInstr *, 4> BlockISELList; - typedef SmallDenseMap<int, BlockISELList> ISELInstructionList; - - // A map of MBB numbers to their lists of contained ISEL instructions. - // Please note when we traverse this list and expand ISEL, we only remove - // the ISEL from the MBB not from this list. - ISELInstructionList ISELInstructions; - - /// Initialize the object. - void initialize(MachineFunction &MFParam); - - void handleSpecialCases(BlockISELList &BIL, MachineBasicBlock *MBB); - void reorganizeBlockLayout(BlockISELList &BIL, MachineBasicBlock *MBB); - void populateBlocks(BlockISELList &BIL); - void expandMergeableISELs(BlockISELList &BIL); - void expandAndMergeISELs(); - - bool canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI); - - /// Is this instruction an ISEL or ISEL8? - static bool isISEL(const MachineInstr &MI) { - return (MI.getOpcode() == PPC::ISEL || MI.getOpcode() == PPC::ISEL8); - } - - /// Is this instruction an ISEL8? - static bool isISEL8(const MachineInstr &MI) { - return (MI.getOpcode() == PPC::ISEL8); - } - - /// Are the two operands using the same register? - bool useSameRegister(const MachineOperand &Op1, const MachineOperand &Op2) { - return (Op1.getReg() == Op2.getReg()); - } - - /// - /// Collect all ISEL instructions from the current function. - /// - /// Walk the current function and collect all the ISEL instructions that are - /// found. The instructions are placed in the ISELInstructions vector. - /// - /// \return true if any ISEL instructions were found, false otherwise - /// - bool collectISELInstructions(); - -public: - static char ID; - PPCExpandISEL() : MachineFunctionPass(ID) { - initializePPCExpandISELPass(*PassRegistry::getPassRegistry()); - } - - /// - /// Determine whether to generate the ISEL instruction or expand it. - /// - /// Expand ISEL instruction into if-then-else sequence when one of - /// the following two conditions hold: - /// (1) -ppc-gen-isel=false - /// (2) hasISEL() return false - /// Otherwise, still generate ISEL instruction. - /// The -ppc-gen-isel option is set to true by default. Which means the ISEL - /// instruction is still generated by default on targets that support them. - /// - /// \return true if ISEL should be expanded into if-then-else code sequence; - /// false if ISEL instruction should be generated, i.e. not expanded. - /// - static bool isExpandISELEnabled(const MachineFunction &MF); - -#ifndef NDEBUG - void DumpISELInstructions() const; -#endif - - bool runOnMachineFunction(MachineFunction &MF) override { - LLVM_DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n"); - initialize(MF); - - if (!collectISELInstructions()) { - LLVM_DEBUG(dbgs() << "No ISEL instructions in this function\n"); - return false; - } - -#ifndef NDEBUG - DumpISELInstructions(); -#endif - - expandAndMergeISELs(); - - return true; - } -}; -} // end anonymous namespace - -void PPCExpandISEL::initialize(MachineFunction &MFParam) { - MF = &MFParam; - TII = MF->getSubtarget().getInstrInfo(); - ISELInstructions.clear(); -} - -bool PPCExpandISEL::isExpandISELEnabled(const MachineFunction &MF) { - return !GenerateISEL || !MF.getSubtarget<PPCSubtarget>().hasISEL(); -} - -bool PPCExpandISEL::collectISELInstructions() { - for (MachineBasicBlock &MBB : *MF) { - BlockISELList thisBlockISELs; - for (MachineInstr &MI : MBB) - if (isISEL(MI)) - thisBlockISELs.push_back(&MI); - if (!thisBlockISELs.empty()) - ISELInstructions.insert(std::make_pair(MBB.getNumber(), thisBlockISELs)); - } - return !ISELInstructions.empty(); -} - -#ifndef NDEBUG -void PPCExpandISEL::DumpISELInstructions() const { - for (const auto &I : ISELInstructions) { - LLVM_DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first)) - << ":\n"); - for (const auto &VI : I.second) - LLVM_DEBUG(dbgs() << " "; VI->print(dbgs())); - } -} -#endif - -/// Contiguous ISELs that have the same condition can be merged. -bool PPCExpandISEL::canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI) { - // Same Condition Register? - if (!useSameRegister(PrevPushedMI->getOperand(3), MI->getOperand(3))) - return false; - - MachineBasicBlock::iterator PrevPushedMBBI = *PrevPushedMI; - MachineBasicBlock::iterator MBBI = *MI; - return (std::prev(MBBI) == PrevPushedMBBI); // Contiguous ISELs? -} - -void PPCExpandISEL::expandAndMergeISELs() { - bool ExpandISELEnabled = isExpandISELEnabled(*MF); - - for (auto &BlockList : ISELInstructions) { - LLVM_DEBUG( - dbgs() << "Expanding ISEL instructions in " - << printMBBReference(*MF->getBlockNumbered(BlockList.first)) - << "\n"); - BlockISELList &CurrentISELList = BlockList.second; - auto I = CurrentISELList.begin(); - auto E = CurrentISELList.end(); - - while (I != E) { - assert(isISEL(**I) && "Expecting an ISEL instruction"); - MachineOperand &Dest = (*I)->getOperand(0); - MachineOperand &TrueValue = (*I)->getOperand(1); - MachineOperand &FalseValue = (*I)->getOperand(2); - - // Special case 1, all registers used by ISEL are the same one. - // The non-redundant isel 0, 0, 0, N would not satisfy these conditions - // as it would be ISEL %R0, %ZERO, %R0, %CRN. - if (useSameRegister(Dest, TrueValue) && - useSameRegister(Dest, FalseValue)) { - LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction: " << **I - << "\n"); - // FIXME: if the CR field used has no other uses, we could eliminate the - // instruction that defines it. This would have to be done manually - // since this pass runs too late to run DCE after it. - NumRemoved++; - (*I)->eraseFromParent(); - I++; - } else if (useSameRegister(TrueValue, FalseValue)) { - // Special case 2, the two input registers used by ISEL are the same. - // Note: the non-foldable isel RX, 0, 0, N would not satisfy this - // condition as it would be ISEL %RX, %ZERO, %R0, %CRN, which makes it - // safe to fold ISEL to MR(OR) instead of ADDI. - MachineBasicBlock *MBB = (*I)->getParent(); - LLVM_DEBUG( - dbgs() << "Fold the ISEL instruction to an unconditional copy:\n"); - LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n"); - NumFolded++; - // Note: we're using both the TrueValue and FalseValue operands so as - // not to lose the kill flag if it is set on either of them. - BuildMI(*MBB, (*I), dl, TII->get(isISEL8(**I) ? PPC::OR8 : PPC::OR)) - .add(Dest) - .add(TrueValue) - .add(FalseValue); - (*I)->eraseFromParent(); - I++; - } else if (ExpandISELEnabled) { // Normal cases expansion enabled - LLVM_DEBUG(dbgs() << "Expand ISEL instructions:\n"); - LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n"); - BlockISELList SubISELList; - SubISELList.push_back(*I++); - // Collect the ISELs that can be merged together. - // This will eat up ISEL instructions without considering whether they - // may be redundant or foldable to a register copy. So we still keep - // the handleSpecialCases() downstream to handle them. - while (I != E && canMerge(SubISELList.back(), *I)) { - LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n"); - SubISELList.push_back(*I++); - } - - expandMergeableISELs(SubISELList); - } else { // Normal cases expansion disabled - I++; // leave the ISEL as it is - } - } // end while - } // end for -} - -void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL, - MachineBasicBlock *MBB) { - IsTrueBlockRequired = false; - IsFalseBlockRequired = false; - - auto MI = BIL.begin(); - while (MI != BIL.end()) { - assert(isISEL(**MI) && "Expecting an ISEL instruction"); - LLVM_DEBUG(dbgs() << "ISEL: " << **MI << "\n"); - - MachineOperand &Dest = (*MI)->getOperand(0); - MachineOperand &TrueValue = (*MI)->getOperand(1); - MachineOperand &FalseValue = (*MI)->getOperand(2); - - // If at least one of the ISEL instructions satisfy the following - // condition, we need the True Block: - // The Dest Register and True Value Register are not the same - // Similarly, if at least one of the ISEL instructions satisfy the - // following condition, we need the False Block: - // The Dest Register and False Value Register are not the same. - bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue); - bool IsORIInstRequired = !useSameRegister(Dest, FalseValue); - - // Special case 1, all registers used by ISEL are the same one. - if (!IsADDIInstRequired && !IsORIInstRequired) { - LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction."); - // FIXME: if the CR field used has no other uses, we could eliminate the - // instruction that defines it. This would have to be done manually - // since this pass runs too late to run DCE after it. - NumRemoved++; - (*MI)->eraseFromParent(); - // Setting MI to the erase result keeps the iterator valid and increased. - MI = BIL.erase(MI); - continue; - } - - // Special case 2, the two input registers used by ISEL are the same. - // Note 1: We favor merging ISEL expansions over folding a single one. If - // the passed list has multiple merge-able ISEL's, we won't fold any. - // Note 2: There is no need to test for PPC::R0/PPC::X0 because PPC::ZERO/ - // PPC::ZERO8 will be used for the first operand if the value is meant to - // be zero. In this case, the useSameRegister method will return false, - // thereby preventing this ISEL from being folded. - if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) { - LLVM_DEBUG( - dbgs() << "Fold the ISEL instruction to an unconditional copy."); - NumFolded++; - // Note: we're using both the TrueValue and FalseValue operands so as - // not to lose the kill flag if it is set on either of them. - BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::OR8 : PPC::OR)) - .add(Dest) - .add(TrueValue) - .add(FalseValue); - (*MI)->eraseFromParent(); - // Setting MI to the erase result keeps the iterator valid and increased. - MI = BIL.erase(MI); - continue; - } - - IsTrueBlockRequired |= IsADDIInstRequired; - IsFalseBlockRequired |= IsORIInstRequired; - MI++; - } -} - -void PPCExpandISEL::reorganizeBlockLayout(BlockISELList &BIL, - MachineBasicBlock *MBB) { - if (BIL.empty()) - return; - - assert((IsTrueBlockRequired || IsFalseBlockRequired) && - "Should have been handled by special cases earlier!"); - - MachineBasicBlock *Successor = nullptr; - const BasicBlock *LLVM_BB = MBB->getBasicBlock(); - MachineBasicBlock::iterator MBBI = (*BIL.back()); - NewSuccessor = (MBBI != MBB->getLastNonDebugInstr() || !MBB->canFallThrough()) - // Another BB is needed to move the instructions that - // follow this ISEL. If the ISEL is the last instruction - // in a block that can't fall through, we also need a block - // to branch to. - ? MF->CreateMachineBasicBlock(LLVM_BB) - : nullptr; - - MachineFunction::iterator It = MBB->getIterator(); - ++It; // Point to the successor block of MBB. - - // If NewSuccessor is NULL then the last ISEL in this group is the last - // non-debug instruction in this block. Find the fall-through successor - // of this block to use when updating the CFG below. - if (!NewSuccessor) { - for (auto &Succ : MBB->successors()) { - if (MBB->isLayoutSuccessor(Succ)) { - Successor = Succ; - break; - } - } - } else - Successor = NewSuccessor; - - // The FalseBlock and TrueBlock are inserted after the MBB block but before - // its successor. - // Note this need to be done *after* the above setting the Successor code. - if (IsFalseBlockRequired) { - FalseBlock = MF->CreateMachineBasicBlock(LLVM_BB); - MF->insert(It, FalseBlock); - } - - if (IsTrueBlockRequired) { - TrueBlock = MF->CreateMachineBasicBlock(LLVM_BB); - MF->insert(It, TrueBlock); - } - - if (NewSuccessor) { - MF->insert(It, NewSuccessor); - - // Transfer the rest of this block into the new successor block. - NewSuccessor->splice(NewSuccessor->end(), MBB, - std::next(MachineBasicBlock::iterator(BIL.back())), - MBB->end()); - NewSuccessor->transferSuccessorsAndUpdatePHIs(MBB); - - // Update the liveins for NewSuccessor. - LivePhysRegs LPR; - computeAndAddLiveIns(LPR, *NewSuccessor); - - } else { - // Remove successor from MBB. - MBB->removeSuccessor(Successor); - } - - // Note that this needs to be done *after* transfering the successors from MBB - // to the NewSuccessor block, otherwise these blocks will also be transferred - // as successors! - MBB->addSuccessor(IsTrueBlockRequired ? TrueBlock : Successor); - MBB->addSuccessor(IsFalseBlockRequired ? FalseBlock : Successor); - - if (IsTrueBlockRequired) { - TrueBlockI = TrueBlock->begin(); - TrueBlock->addSuccessor(Successor); - } - - if (IsFalseBlockRequired) { - FalseBlockI = FalseBlock->begin(); - FalseBlock->addSuccessor(Successor); - } - - // Conditional branch to the TrueBlock or Successor - BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC)) - .add(BIL.back()->getOperand(3)) - .addMBB(IsTrueBlockRequired ? TrueBlock : Successor); - - // Jump over the true block to the new successor if the condition is false. - BuildMI(*(IsFalseBlockRequired ? FalseBlock : MBB), - (IsFalseBlockRequired ? FalseBlockI : BIL.back()), dl, - TII->get(PPC::B)) - .addMBB(Successor); - - if (IsFalseBlockRequired) - FalseBlockI = FalseBlock->begin(); // get the position of PPC::B -} - -void PPCExpandISEL::populateBlocks(BlockISELList &BIL) { - for (auto &MI : BIL) { - assert(isISEL(*MI) && "Expecting an ISEL instruction"); - - MachineOperand &Dest = MI->getOperand(0); // location to store to - MachineOperand &TrueValue = MI->getOperand(1); // Value to store if - // condition is true - MachineOperand &FalseValue = MI->getOperand(2); // Value to store if - // condition is false - - LLVM_DEBUG(dbgs() << "Dest: " << Dest << "\n"); - LLVM_DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n"); - LLVM_DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n"); - LLVM_DEBUG(dbgs() << "ConditionRegister: " << MI->getOperand(3) << "\n"); - - // If the Dest Register and True Value Register are not the same one, we - // need the True Block. - bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue); - bool IsORIInstRequired = !useSameRegister(Dest, FalseValue); - - // Copy the result into the destination if the condition is true. - if (IsADDIInstRequired) - BuildMI(*TrueBlock, TrueBlockI, dl, - TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI)) - .add(Dest) - .add(TrueValue) - .add(MachineOperand::CreateImm(0)); - - // Copy the result into the destination if the condition is false. - if (IsORIInstRequired) - BuildMI(*FalseBlock, FalseBlockI, dl, - TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI)) - .add(Dest) - .add(FalseValue) - .add(MachineOperand::CreateImm(0)); - - MI->eraseFromParent(); // Remove the ISEL instruction. - - NumExpanded++; - } - - if (IsTrueBlockRequired) { - // Update the liveins for TrueBlock. - LivePhysRegs LPR; - computeAndAddLiveIns(LPR, *TrueBlock); - } - - if (IsFalseBlockRequired) { - // Update the liveins for FalseBlock. - LivePhysRegs LPR; - computeAndAddLiveIns(LPR, *FalseBlock); - } -} - -void PPCExpandISEL::expandMergeableISELs(BlockISELList &BIL) { - // At this stage all the ISELs of BIL are in the same MBB. - MachineBasicBlock *MBB = BIL.back()->getParent(); - - handleSpecialCases(BIL, MBB); - reorganizeBlockLayout(BIL, MBB); - populateBlocks(BIL); -} - -INITIALIZE_PASS(PPCExpandISEL, DEBUG_TYPE, "PowerPC Expand ISEL Generation", - false, false) -char PPCExpandISEL::ID = 0; - -FunctionPass *llvm::createPPCExpandISELPass() { return new PPCExpandISEL(); } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 6ce345dd4413..7d0455942923 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -141,7 +141,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() { initializePPCBSelPass(PR); initializePPCBranchCoalescingPass(PR); initializePPCBoolRetToIntPass(PR); - initializePPCExpandISELPass(PR); initializePPCPreEmitPeepholePass(PR); initializePPCTLSDynamicCallPass(PR); initializePPCMIPeepholePass(PR); @@ -600,7 +599,6 @@ void PPCPassConfig::addPreSched2() { void PPCPassConfig::addPreEmitPass() { addPass(createPPCPreEmitPeepholePass()); - addPass(createPPCExpandISELPass()); if (getOptLevel() != CodeGenOptLevel::None) addPass(createPPCEarlyReturnPass()); diff --git a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll index 70b421f8c0c5..4a17384e4999 100644 --- a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll +++ b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll @@ -59,7 +59,6 @@ ; CHECK-NEXT: Insert XRay ops ; CHECK-NEXT: Implement the 'patchable-function' attribute ; CHECK-NEXT: PowerPC Pre-Emit Peephole -; CHECK-NEXT: PowerPC Expand ISEL Generation ; CHECK-NEXT: Contiguously Lay Out Funclets ; CHECK-NEXT: StackMap Liveness Analysis ; CHECK-NEXT: Live DEBUG_VALUE analysis diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll index 60d42704ca79..39b23a57513d 100644 --- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll +++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll @@ -212,7 +212,6 @@ ; CHECK-NEXT: Insert XRay ops ; CHECK-NEXT: Implement the 'patchable-function' attribute ; CHECK-NEXT: PowerPC Pre-Emit Peephole -; CHECK-NEXT: PowerPC Expand ISEL Generation ; CHECK-NEXT: PowerPC Early-Return Creation ; CHECK-NEXT: Contiguously Lay Out Funclets ; CHECK-NEXT: StackMap Liveness Analysis diff --git a/llvm/test/CodeGen/PowerPC/crbit-asm.ll b/llvm/test/CodeGen/PowerPC/crbit-asm.ll index 617d6ec27b63..2062aa3e3441 100644 --- a/llvm/test/CodeGen/PowerPC/crbit-asm.ll +++ b/llvm/test/CodeGen/PowerPC/crbit-asm.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s -; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -26,15 +26,13 @@ define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 { ; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1 ; CHECK-NO-ISEL-NEXT: crmove 20, 1 ; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1 -; CHECK-NO-ISEL-NEXT: li 3, 0 -; CHECK-NO-ISEL-NEXT: li 4, 1 +; CHECK-NO-ISEL-NEXT: li 3, 1 ; CHECK-NO-ISEL-NEXT: #APP ; CHECK-NO-ISEL-NEXT: crand 20, 20, 1 ; CHECK-NO-ISEL-NEXT: #NO_APP -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_1 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 +; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 0 ; CHECK-NO-ISEL-NEXT: blr entry: %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0 @@ -63,15 +61,13 @@ define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 { ; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1 ; CHECK-NO-ISEL-NEXT: crmove 20, 1 ; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1 -; CHECK-NO-ISEL-NEXT: li 3, 0 -; CHECK-NO-ISEL-NEXT: li 4, -1 +; CHECK-NO-ISEL-NEXT: li 3, -1 ; CHECK-NO-ISEL-NEXT: #APP ; CHECK-NO-ISEL-NEXT: crand 20, 20, 1 ; CHECK-NO-ISEL-NEXT: #NO_APP -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_1 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 +; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 0 ; CHECK-NO-ISEL-NEXT: blr entry: %0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0 @@ -101,15 +97,13 @@ define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 { ; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1 ; CHECK-NO-ISEL-NEXT: crmove 20, 1 ; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1 -; CHECK-NO-ISEL-NEXT: li 3, 0 -; CHECK-NO-ISEL-NEXT: li 4, 1 +; CHECK-NO-ISEL-NEXT: li 3, 1 ; CHECK-NO-ISEL-NEXT: #APP ; CHECK-NO-ISEL-NEXT: crand 20, 20, 1 ; CHECK-NO-ISEL-NEXT: #NO_APP -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_1 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB2_1: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 +; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 0 ; CHECK-NO-ISEL-NEXT: blr entry: %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0 diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll index a682f69a2ceb..763f596777a6 100644 --- a/llvm/test/CodeGen/PowerPC/crbits.ll +++ b/llvm/test/CodeGen/PowerPC/crbits.ll @@ -2,7 +2,7 @@ ; RUN: llc -ppc-gpr-icmps=all -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-gpr-icmps=all -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | \ +; RUN: -verify-machineinstrs -mcpu=pwr7 -mattr=-isel < %s | \ ; RUN: FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 -ppc-gpr-icmps=none < %s | \ @@ -30,16 +30,16 @@ define zeroext i1 @test1(float %v1, float %v2) #0 { ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2 ; CHECK-NO-ISEL-NEXT: xxlxor 0, 0, 0 -; CHECK-NO-ISEL-NEXT: li 3, 1 +; CHECK-NO-ISEL-NEXT: li 3, 0 ; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 2 ; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0 ; CHECK-NO-ISEL-NEXT: fcmpu 0, 2, 0 -; CHECK-NO-ISEL-NEXT: crnor 21, 7, 1 -; CHECK-NO-ISEL-NEXT: crnand 20, 20, 21 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_1 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry -; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: bclr 4, 20, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: crnor 20, 7, 1 +; CHECK-NO-ISEL-NEXT: bclr 4, 20, 0 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 1 ; CHECK-NO-ISEL-NEXT: blr ; ; CHECK-P10-LABEL: test1: @@ -81,16 +81,15 @@ define zeroext i1 @test2(float %v1, float %v2) #0 { ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2 ; CHECK-NO-ISEL-NEXT: xxlxor 0, 0, 0 -; CHECK-NO-ISEL-NEXT: li 3, 1 +; CHECK-NO-ISEL-NEXT: li 3, 0 ; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 2 ; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0 ; CHECK-NO-ISEL-NEXT: fcmpu 0, 2, 0 ; CHECK-NO-ISEL-NEXT: crnor 21, 7, 1 ; CHECK-NO-ISEL-NEXT: creqv 20, 20, 21 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_1 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry -; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 1 ; CHECK-NO-ISEL-NEXT: blr ; ; CHECK-P10-LABEL: test2: @@ -134,7 +133,7 @@ define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 { ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2 ; CHECK-NO-ISEL-NEXT: xxlxor 0, 0, 0 -; CHECK-NO-ISEL-NEXT: li 3, 1 +; CHECK-NO-ISEL-NEXT: li 3, 0 ; CHECK-NO-ISEL-NEXT: fcmpu 1, 2, 2 ; CHECK-NO-ISEL-NEXT: crnor 20, 3, 0 ; CHECK-NO-ISEL-NEXT: fcmpu 0, 2, 0 @@ -142,10 +141,9 @@ define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 { ; CHECK-NO-ISEL-NEXT: cmpwi 5, -2 ; CHECK-NO-ISEL-NEXT: crandc 21, 21, 2 ; CHECK-NO-ISEL-NEXT: creqv 20, 20, 21 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_1 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB2_1: # %entry -; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 1 ; CHECK-NO-ISEL-NEXT: blr ; ; CHECK-P10-LABEL: test3: @@ -301,10 +299,9 @@ define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 { ; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1 ; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB6_2 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 5, 0 -; CHECK-NO-ISEL-NEXT: blr +; CHECK-NO-ISEL-NEXT: mr 4, 5 ; CHECK-NO-ISEL-NEXT: .LBB6_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr ; ; CHECK-P10-LABEL: test7: @@ -330,12 +327,10 @@ define signext i32 @exttest7(i32 signext %a) #0 { ; CHECK-NO-ISEL-LABEL: exttest7: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmplwi 3, 5 +; CHECK-NO-ISEL-NEXT: li 3, 7 +; CHECK-NO-ISEL-NEXT: beqlr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry ; CHECK-NO-ISEL-NEXT: li 3, 8 -; CHECK-NO-ISEL-NEXT: li 4, 7 -; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB7_1 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB7_1: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 ; CHECK-NO-ISEL-NEXT: blr ; ; CHECK-P10-LABEL: exttest7: @@ -366,15 +361,15 @@ define zeroext i32 @exttest8() #0 { ; CHECK-NO-ISEL-LABEL: exttest8: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: ld 3, 0(3) +; CHECK-NO-ISEL-NEXT: li 4, 0 ; CHECK-NO-ISEL-NEXT: subfic 3, 3, 80 ; CHECK-NO-ISEL-NEXT: rldicl 3, 3, 63, 1 ; CHECK-NO-ISEL-NEXT: cmplwi 3, 80 -; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB8_1 -; CHECK-NO-ISEL-NEXT: b .LBB8_2 -; CHECK-NO-ISEL-NEXT: .LBB8_1: # %entry -; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: bgt 0, .LBB8_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 4, 3 ; CHECK-NO-ISEL-NEXT: .LBB8_2: # %entry -; CHECK-NO-ISEL-NEXT: clrldi 3, 3, 32 +; CHECK-NO-ISEL-NEXT: clrldi 3, 4, 32 ; CHECK-NO-ISEL-NEXT: blr ; ; CHECK-P10-LABEL: exttest8: diff --git a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll index 15b7dc1a38fa..9e53c7e88b0e 100644 --- a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll +++ b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" ; This file mainly tests that one of the ISEL instruction in the group uses the same register for operand RT, RA, RB @@ -13,8 +14,8 @@ target triple = "powerpc64le-unknown-linux-gnu" ; After that we have: ; updated: 1504B %vreg83<def> = ISEL8 %vreg83, %vreg83, %vreg33:sub_eq -; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE -; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel +; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=+isel < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE +; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=-isel < %s | FileCheck %s --implicit-check-not isel @.str = private unnamed_addr constant [3 x i8] c"]]\00", align 1 @.str.1 = private unnamed_addr constant [35 x i8] c"Index < Length && \22Invalid index!\22\00", align 1 @@ -23,6 +24,219 @@ target triple = "powerpc64le-unknown-linux-gnu" @.str.3 = private unnamed_addr constant [95 x i8] c"(data || length == 0) && \22StringRef cannot be built from a NULL argument with non-null length\22\00", align 1 @__PRETTY_FUNCTION__._ZN4llvm9StringRefC2EPKcm = private unnamed_addr constant [49 x i8] c"llvm::StringRef::StringRef(const char *, size_t)\00", align 1 define i64 @_Z3fn1N4llvm9StringRefE([2 x i64] %Str.coerce) { +; CHECK-GEN-ISEL-TRUE-LABEL: _Z3fn1N4llvm9StringRefE: +; CHECK-GEN-ISEL-TRUE: # %bb.0: # %entry +; CHECK-GEN-ISEL-TRUE-NEXT: mflr r0 +; CHECK-GEN-ISEL-TRUE-NEXT: stdu r1, -32(r1) +; CHECK-GEN-ISEL-TRUE-NEXT: std r0, 48(r1) +; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_def_cfa_offset 32 +; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset lr, 16 +; CHECK-GEN-ISEL-TRUE-NEXT: li r5, 2 +; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x6 +; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_3 +; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 4 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %_ZNK4llvm9StringRefixEm.exit +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r7, 93 +; CHECK-GEN-ISEL-TRUE-NEXT: addi r7, r6, -1 +; CHECK-GEN-ISEL-TRUE-NEXT: iseleq r6, r7, r6 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_2: # %_ZNK4llvm9StringRef6substrEmm.exit +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r4, -1 +; CHECK-GEN-ISEL-TRUE-NEXT: addi r3, r3, 1 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_3: # %while.cond.outer +; CHECK-GEN-ISEL-TRUE-NEXT: # =>This Loop Header: Depth=1 +; CHECK-GEN-ISEL-TRUE-NEXT: # Child Loop BB0_5 Depth 2 +; CHECK-GEN-ISEL-TRUE-NEXT: # Child Loop BB0_8 Depth 2 +; CHECK-GEN-ISEL-TRUE-NEXT: cmpldi r6, 0 +; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_8 +; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.4: # %while.cond.preheader +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: cmpldi r4, 0 +; CHECK-GEN-ISEL-TRUE-NEXT: beq- cr0, .LBB0_15 +; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 5 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_5: # %_ZNK4llvm9StringRefixEm.exit +; CHECK-GEN-ISEL-TRUE-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-GEN-ISEL-TRUE-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-GEN-ISEL-TRUE-NEXT: lbz r7, 0(r3) +; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r7, 92 +; CHECK-GEN-ISEL-TRUE-NEXT: bne cr0, .LBB0_1 +; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.6: # %if.then4 +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: cmpldi r4, 2 +; CHECK-GEN-ISEL-TRUE-NEXT: isellt r7, r4, r5 +; CHECK-GEN-ISEL-TRUE-NEXT: add r3, r3, r7 +; CHECK-GEN-ISEL-TRUE-NEXT: sub. r4, r4, r7 +; CHECK-GEN-ISEL-TRUE-NEXT: bne+ cr0, .LBB0_5 +; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_15 +; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 5 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_7: # %if.then4.us +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: isellt r6, r4, r5 +; CHECK-GEN-ISEL-TRUE-NEXT: add r3, r3, r6 +; CHECK-GEN-ISEL-TRUE-NEXT: sub r4, r4, r6 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_8: # %while.cond.us +; CHECK-GEN-ISEL-TRUE-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-GEN-ISEL-TRUE-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-GEN-ISEL-TRUE-NEXT: cmpldi r4, 2 +; CHECK-GEN-ISEL-TRUE-NEXT: bge cr0, .LBB0_10 +; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.9: # %if.end.us +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: cmpldi cr1, r4, 0 +; CHECK-GEN-ISEL-TRUE-NEXT: bne+ cr1, .LBB0_11 +; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_15 +; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 5 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_10: # %if.end.i.i.us +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: lhz r6, 0(r3) +; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi cr1, r6, 23901 +; CHECK-GEN-ISEL-TRUE-NEXT: beq cr1, .LBB0_14 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_11: # %_ZNK4llvm9StringRefixEm.exit.us +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: lbz r6, 0(r3) +; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi cr1, r6, 92 +; CHECK-GEN-ISEL-TRUE-NEXT: beq cr1, .LBB0_7 +; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.12: # %_ZNK4llvm9StringRefixEm.exit.us +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r6, 93 +; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_16 +; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.13: # %_ZNK4llvm9StringRef6substrEmm.exit.loopexit +; CHECK-GEN-ISEL-TRUE-NEXT: # +; CHECK-GEN-ISEL-TRUE-NEXT: li r6, 0 +; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_2 +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_14: # %if.then +; CHECK-GEN-ISEL-TRUE-NEXT: addi r1, r1, 32 +; CHECK-GEN-ISEL-TRUE-NEXT: ld r0, 16(r1) +; CHECK-GEN-ISEL-TRUE-NEXT: mtlr r0 +; CHECK-GEN-ISEL-TRUE-NEXT: blr +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_15: # %cond.false.i +; CHECK-GEN-ISEL-TRUE-NEXT: addis r3, r2, .L__ModuleStringPool@toc@ha +; CHECK-GEN-ISEL-TRUE-NEXT: li r5, 225 +; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r3, .L__ModuleStringPool@toc@l +; CHECK-GEN-ISEL-TRUE-NEXT: addi r3, r4, 53 +; CHECK-GEN-ISEL-TRUE-NEXT: addi r6, r4, 88 +; CHECK-GEN-ISEL-TRUE-NEXT: bl __assert_fail +; CHECK-GEN-ISEL-TRUE-NEXT: nop +; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_16: # %if.then9 +; CHECK-GEN-ISEL-TRUE-NEXT: li r3, 1 +; CHECK-GEN-ISEL-TRUE-NEXT: bl exit +; CHECK-GEN-ISEL-TRUE-NEXT: nop +; +; CHECK-LABEL: _Z3fn1N4llvm9StringRefE: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: stdu r1, -32(r1) +; CHECK-NEXT: std r0, 48(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: # implicit-def: $x5 +; CHECK-NEXT: b .LBB0_2 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_1: # %_ZNK4llvm9StringRef6substrEmm.exit +; CHECK-NEXT: # +; CHECK-NEXT: addi r4, r4, -1 +; CHECK-NEXT: addi r3, r3, 1 +; CHECK-NEXT: .LBB0_2: # %while.cond.outer +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB0_5 Depth 2 +; CHECK-NEXT: # Child Loop BB0_9 Depth 2 +; CHECK-NEXT: cmpldi r5, 0 +; CHECK-NEXT: beq cr0, .LBB0_9 +; CHECK-NEXT: # %bb.3: # %while.cond.preheader +; CHECK-NEXT: # +; CHECK-NEXT: cmpldi r4, 0 +; CHECK-NEXT: bne+ cr0, .LBB0_5 +; CHECK-NEXT: b .LBB0_20 +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB0_4: # %if.then4 +; CHECK-NEXT: # +; CHECK-NEXT: add r3, r3, r6 +; CHECK-NEXT: sub. r4, r4, r6 +; CHECK-NEXT: beq- cr0, .LBB0_20 +; CHECK-NEXT: .LBB0_5: # %_ZNK4llvm9StringRefixEm.exit +; CHECK-NEXT: # Parent Loop BB0_2 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: lbz r6, 0(r3) +; CHECK-NEXT: cmplwi r6, 92 +; CHECK-NEXT: bne cr0, .LBB0_15 +; CHECK-NEXT: # %bb.6: # %if.then4 +; CHECK-NEXT: # +; CHECK-NEXT: cmpldi r4, 2 +; CHECK-NEXT: mr r6, r4 +; CHECK-NEXT: blt cr0, .LBB0_4 +; CHECK-NEXT: # %bb.7: # %if.then4 +; CHECK-NEXT: # +; CHECK-NEXT: li r6, 2 +; CHECK-NEXT: b .LBB0_4 +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB0_8: # %if.then4.us +; CHECK-NEXT: # +; CHECK-NEXT: add r3, r3, r5 +; CHECK-NEXT: sub r4, r4, r5 +; CHECK-NEXT: .LBB0_9: # %while.cond.us +; CHECK-NEXT: # Parent Loop BB0_2 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: cmpldi r4, 2 +; CHECK-NEXT: bge cr0, .LBB0_11 +; CHECK-NEXT: # %bb.10: # %if.end.us +; CHECK-NEXT: # +; CHECK-NEXT: cmpldi cr1, r4, 0 +; CHECK-NEXT: bne+ cr1, .LBB0_12 +; CHECK-NEXT: b .LBB0_20 +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB0_11: # %if.end.i.i.us +; CHECK-NEXT: # +; CHECK-NEXT: lhz r5, 0(r3) +; CHECK-NEXT: cmplwi cr1, r5, 23901 +; CHECK-NEXT: beq cr1, .LBB0_19 +; CHECK-NEXT: .LBB0_12: # %_ZNK4llvm9StringRefixEm.exit.us +; CHECK-NEXT: # +; CHECK-NEXT: lbz r5, 0(r3) +; CHECK-NEXT: cmplwi cr1, r5, 92 +; CHECK-NEXT: bne cr1, .LBB0_17 +; CHECK-NEXT: # %bb.13: # %if.then4.us +; CHECK-NEXT: # +; CHECK-NEXT: mr r5, r4 +; CHECK-NEXT: bc 12, lt, .LBB0_8 +; CHECK-NEXT: # %bb.14: # %if.then4.us +; CHECK-NEXT: # +; CHECK-NEXT: li r5, 2 +; CHECK-NEXT: b .LBB0_8 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_15: # %_ZNK4llvm9StringRefixEm.exit +; CHECK-NEXT: # +; CHECK-NEXT: cmplwi r6, 93 +; CHECK-NEXT: bne cr0, .LBB0_1 +; CHECK-NEXT: # %bb.16: # %if.end10 +; CHECK-NEXT: # +; CHECK-NEXT: addi r5, r5, -1 +; CHECK-NEXT: b .LBB0_1 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_17: # %_ZNK4llvm9StringRefixEm.exit.us +; CHECK-NEXT: # +; CHECK-NEXT: cmplwi r5, 93 +; CHECK-NEXT: beq cr0, .LBB0_21 +; CHECK-NEXT: # %bb.18: # %_ZNK4llvm9StringRef6substrEmm.exit.loopexit +; CHECK-NEXT: # +; CHECK-NEXT: li r5, 0 +; CHECK-NEXT: b .LBB0_1 +; CHECK-NEXT: .LBB0_19: # %if.then +; CHECK-NEXT: addi r1, r1, 32 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +; CHECK-NEXT: .LBB0_20: # %cond.false.i +; CHECK-NEXT: addis r3, r2, .L__ModuleStringPool@toc@ha +; CHECK-NEXT: li r5, 225 +; CHECK-NEXT: addi r4, r3, .L__ModuleStringPool@toc@l +; CHECK-NEXT: addi r3, r4, 53 +; CHECK-NEXT: addi r6, r4, 88 +; CHECK-NEXT: bl __assert_fail +; CHECK-NEXT: nop +; CHECK-NEXT: .LBB0_21: # %if.then9 +; CHECK-NEXT: li r3, 1 +; CHECK-NEXT: bl exit +; CHECK-NEXT: nop entry: %Str.coerce.fca.0.extract = extractvalue [2 x i64] %Str.coerce, 0 %Str.coerce.fca.1.extract = extractvalue [2 x i64] %Str.coerce, 1 @@ -130,16 +344,7 @@ _ZNK4llvm9StringRef6substrEmm.exit: %8 = ptrtoint ptr %add.ptr.i to i64 br label %while.cond.outer -; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE ; Unecessary ISEL (all the registers are the same) is always removed -; CHECK-GEN-ISEL-TRUE-NOT: iseleq [[SAME:r[0-9]+]], [[SAME]], [[SAME]] -; CHECK-GEN-ISEL-TRUE: iseleq [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]] -; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]] -; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: # in Loop: Header -; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0 -; CHECK-NEXT: [[SUCCESSOR]] } diff --git a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll index 8da7519fa6dc..5425996032e3 100644 --- a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll +++ b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll @@ -15,8 +15,8 @@ target triple = "powerpc64le-unknown-linux-gnu" ; After that we have: ; updated: 416B %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>; -; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE -; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel +; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=+isel < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE +; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=-isel < %s | FileCheck %s --implicit-check-not isel %"struct.pov::ot_block_struct" = type { ptr, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 } %"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", ptr, [8 x ptr] } %"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 } diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-1.mir b/llvm/test/CodeGen/PowerPC/expand-isel-1.mir deleted file mode 100644 index 35e539807052..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-1.mir +++ /dev/null @@ -1,57 +0,0 @@ -# This file tests the scenario: ISEL R0, ZERO, R0, CR -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x0' } - - { reg: '$x3' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x0, $x3 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r0 = ISEL $zero, $r0, $cr0gt - ; CHECK-LABEL: testExpandISEL - ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK-NEXT: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r0 = ADDI $zero, 0 - - $x3 = EXTSW_32_64 $r0 - -... - diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-10.mir b/llvm/test/CodeGen/PowerPC/expand-isel-10.mir deleted file mode 100644 index 6d51246336c2..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-10.mir +++ /dev/null @@ -1,54 +0,0 @@ -# This file tests the scenario: ISEL RX, RX, RX, CR (X != 0), -# which is redudant and removed. -# RUN: llc -ppc-gen-isel=true -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x3' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x3 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r3 = ISEL $r3, $r3, $cr0gt - $x3 = EXTSW_32_64 $r3 - ; CHECK: $r5 = ADDI $r3, 1 - ; CHECK: $cr0 = CMPWI $r3, 0 - ; CHECK-NOT: $r3 = ISEL $r3, $r3, $cr0gt - ; CHECK: $x3 = EXTSW_32_64 $r3 - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-2.mir b/llvm/test/CodeGen/PowerPC/expand-isel-2.mir deleted file mode 100644 index a4265e07f81e..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-2.mir +++ /dev/null @@ -1,57 +0,0 @@ -# This file tests the scenario: ISEL RX, ZERO, RY, CR (X != 0 && Y != 0) -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x0' } - - { reg: '$x3' } - - { reg: '$x4' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x0, $x3, $x4 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r3 = ISEL $zero, $r4, $cr0gt - ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK: %[[FALSE:bb.[0-9]+]] - ; CHECK: $r3 = ORI $r4, 0 - ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r3 = ADDI $zero, 0 - - $x3 = EXTSW_32_64 $r3 -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-3.mir b/llvm/test/CodeGen/PowerPC/expand-isel-3.mir deleted file mode 100644 index 28273602f91e..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-3.mir +++ /dev/null @@ -1,58 +0,0 @@ -# This file tests the scenario: ISEL RX, RY, R0, CR (X != 0 && Y != 0) -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x0' } - - { reg: '$x3' } - - { reg: '$x4' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x0, $x3, $x4 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r3 = ISEL $r4, $r0, $cr0gt - ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK: %[[FALSE:bb.[0-9]+]] - ; CHECK: $r3 = ORI $r0, 0 - ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r3 = ADDI $r4, 0 - - $x3 = EXTSW_32_64 $r3 - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-4.mir b/llvm/test/CodeGen/PowerPC/expand-isel-4.mir deleted file mode 100644 index d4484f6d527c..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-4.mir +++ /dev/null @@ -1,59 +0,0 @@ -# This file tests the scenario: ISEL R0, ZERO, RX, CR (X != 0) -# It also tests redundant liveins ($x7) and killed registers. -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x0' } - - { reg: '$x3' } - - { reg: '$x7' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x0, $x3, $x7 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r0 = ISEL killed $zero, killed $r5, killed $cr0gt, implicit killed $cr0 - ; CHECK: BC killed $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK: %[[FALSE:bb.[0-9]+]] - ; CHECK: $r0 = ORI killed $r5, 0 - ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r0 = ADDI killed $zero, 0 - - $x0 = EXTSW_32_64 killed $r0 - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-5.mir b/llvm/test/CodeGen/PowerPC/expand-isel-5.mir deleted file mode 100644 index 4142ef0fe89e..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-5.mir +++ /dev/null @@ -1,54 +0,0 @@ -# This file tests the scenario: ISEL R0, RX, R0, CR (X != 0) -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x0' } - - { reg: '$x3' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x0, $x3 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r0 = ISEL $r5, $r0, $cr0gt - ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r0 = ADDI $r5, 0 - $x3 = EXTSW_32_64 $r0 - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-6.mir b/llvm/test/CodeGen/PowerPC/expand-isel-6.mir deleted file mode 100644 index 9ab511e69593..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-6.mir +++ /dev/null @@ -1,57 +0,0 @@ -# This file tests the scenario when ISEL is the last instruction of the last -# Basic Block, i.e., the BB cannot fall through to its successor situation. -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x0' } - - { reg: '$x3' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x0, $x3 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r3 = ISEL $zero, $r0, $cr0gt - ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK: %[[FALSE:bb.[0-9]+]] - ; CHECK: $r3 = ORI $r0, 0 - ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r3 = ADDI $zero, 0 - - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-7.mir b/llvm/test/CodeGen/PowerPC/expand-isel-7.mir deleted file mode 100644 index 64c262470000..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-7.mir +++ /dev/null @@ -1,58 +0,0 @@ -# This file tests the scenario: ISEL RX, RY, RZ, CR (X != 0 && Y != 0, Z != 0) -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x3' } - - { reg: '$x4' } - - { reg: '$x5' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x3, $x4, $x5 - - $r4 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r5 = ISEL $r3, $r4, $cr0gt - ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK: %[[FALSE:bb.[0-9]+]] - ; CHECK: $r5 = ORI $r4, 0 - ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r5 = ADDI $r3, 0 - - $x5 = EXTSW_32_64 $r5 - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-8.mir b/llvm/test/CodeGen/PowerPC/expand-isel-8.mir deleted file mode 100644 index 1799676afee7..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-8.mir +++ /dev/null @@ -1,65 +0,0 @@ -# This file tests combining three consecutive ISELs scenario. -# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x3' } - - { reg: '$x4' } - - { reg: '$x5' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x3, $x4, $x5 - - $r4 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r5 = ISEL $r3, $r4, $cr0gt - $r3 = ISEL $r4, $r5, $cr0gt - $r4 = ISEL $r3, $r5, $cr0gt - ; CHECK: BC $cr0gt, %[[TRUE:bb.[0-9]+]] - ; CHECK: %[[FALSE:bb.[0-9]+]] - ; CHECK: $r5 = ORI $r4, 0 - ; CHECK: $r3 = ORI $r5, 0 - ; CHECK: $r4 = ORI $r5, 0 - ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]] - ; CHECK: [[TRUE]] - ; CHECK: $r5 = ADDI $r3, 0 - ; CHECK: $r3 = ADDI $r4, 0 - ; CHECK: $r4 = ADDI $r3, 0 - - $x5 = EXTSW_32_64 $r5 - $x3 = EXTSW_32_64 $r3 - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-9.mir b/llvm/test/CodeGen/PowerPC/expand-isel-9.mir deleted file mode 100644 index 2f0cdca8496b..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-9.mir +++ /dev/null @@ -1,54 +0,0 @@ -# This file tests the scenario: ISEL RX, RY, RY, CR (X != 0 && Y != 0) -# It is folded into a copy (%RX = OR %RY, %RY) -# RUN: llc -ppc-gen-isel=true -run-pass ppc-expand-isel -o - %s | FileCheck %s - ---- | - target datalayout = "E-m:e-i64:64-n32:64" - target triple = "powerpc64-unknown-linux-gnu" - define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) { - entry: - %cmp = icmp sgt i32 %i, 0 - %add = add nsw i32 %i, 1 - %cond = select i1 %cmp, i32 %add, i32 %j - ret i32 %cond - } - -... ---- -name: testExpandISEL -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$x3' } - - { reg: '$x4' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0.entry: - liveins: $x3, $x4 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r3 = ISEL $r4, $r4, $cr0gt - ; Test fold ISEL to a copy - ; CHECK: $r3 = OR $r4, $r4 - - $x3 = EXTSW_32_64 $r3 - -... diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-liveness.mir b/llvm/test/CodeGen/PowerPC/expand-isel-liveness.mir deleted file mode 100644 index 262e71d48fc0..000000000000 --- a/llvm/test/CodeGen/PowerPC/expand-isel-liveness.mir +++ /dev/null @@ -1,80 +0,0 @@ -# RUN: llc -mtriple powerpc64-unknown-linux-gnu -run-pass=ppc-expand-isel -o \ -# RUN: - %s -verify-machineinstrs | FileCheck %s - ---- -name: expand_isel_liveness1 -tracksRegLiveness: true -registers: [] -liveins: - - { reg: '$x3', virtual-reg: '' } - - { reg: '$x4', virtual-reg: '' } - - { reg: '$x5', virtual-reg: '' } - - { reg: '$x6', virtual-reg: '' } -body: | - bb.0: - liveins: $x3, $x4, $x5, $x6 - - renamable $x8 = MULLD renamable $x5, renamable $x4 - renamable $cr5 = CMPDI renamable $x3, 0 - dead renamable $x9 = MULHDU_rec renamable $x3, renamable $x6, implicit-def $cr0 - renamable $x3 = MULLD killed renamable $x3, renamable $x6 - $cr1 = MCRF killed $cr0 - renamable $x3 = ADD8 killed renamable $x3, killed renamable $x8 - renamable $cr0 = CMPDI renamable $x5, 0 - renamable $cr5lt = CRNOR killed renamable $cr0eq, killed renamable $cr5eq, implicit $cr5, implicit $cr0 - renamable $cr0 = CMPLDI renamable $x3, 0 - renamable $x8 = MULHDU renamable $x4, renamable $x6 - renamable $x3 = ADD8 renamable $x8, killed renamable $x3 - renamable $cr6 = CMPLD renamable $x3, killed renamable $x8 - renamable $cr5gt = CRANDC killed renamable $cr6lt, killed renamable $cr0eq, implicit $cr0, implicit $cr6 - renamable $cr5lt = CRORC killed renamable $cr5lt, killed renamable $cr1eq, implicit $cr1 - renamable $x7 = LI8 1 - dead renamable $x5 = MULHDU_rec killed renamable $x5, renamable $x4, implicit-def $cr0 - renamable $cr5lt = CRORC killed renamable $cr5lt, killed renamable $cr0eq, implicit $cr0 - renamable $cr5lt = CRNOR killed renamable $cr5lt, killed renamable $cr5gt - renamable $x4 = MULLD killed renamable $x4, killed renamable $x6 - renamable $x5 = ISEL8 $zero8, killed renamable $x7, killed renamable $cr5lt - BLR8 implicit $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5 - - ; CHECK-LABEL: name: expand_isel_liveness1 - ; CHECK: bb.1: - ; CHECK: liveins: $x3, $x4, $x7 - ; CHECK: renamable $x5 = ORI8 killed renamable $x7, 0 - ; CHECK: B %bb.3 - ; CHECK: bb.2: - ; CHECK: liveins: $x3, $x4 - ; CHECK: renamable $x5 = ADDI8 $zero8, 0 - ; CHECK: bb.3: - ; CHECK: liveins: $x3, $x4, $x5 - ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5 -... - ---- -name: expand_isel_liveness2 -tracksRegLiveness: true -liveins: - - { reg: '$r0' } - - { reg: '$r3' } -body: | - bb.0.entry: - liveins: $r0, $r3 - - $r5 = ADDI $r3, 1 - $cr0 = CMPWI $r3, 0 - $r3 = ISEL $zero, killed $r0, killed $cr0gt - - ; CHECK-LABEL: name: expand_isel_liveness2 - ; CHECK: bb.0.entry: - ; CHECK: liveins: $r0, $r3 - ; CHECK: $r5 = ADDI $r3, 1 - ; CHECK: $cr0 = CMPWI $r3, 0 - ; CHECK: BC killed $cr0gt, %bb.2 - ; CHECK: bb.1.entry: - ; CHECK: liveins: $r0 - ; CHECK: $r3 = ORI killed $r0, 0 - ; CHECK: B %bb.3 - ; CHECK: bb.2.entry: - ; CHECK-NOT: liveins: $zero - ; CHECK: $r3 = ADDI $zero, 0 -... - diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll index cf403d6db14d..16e18b595da1 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel.ll +++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll @@ -1,150 +1,161 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -mattr=-isel < %s | FileCheck %s --implicit-check-not isel define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) { +; CHECK-LABEL: testExpandISELToIfElse: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpwi r3, 0 +; CHECK-NEXT: ble cr0, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: addi r4, r3, 1 +; CHECK-NEXT: .LBB0_2: # %entry +; CHECK-NEXT: extsw r3, r4 +; CHECK-NEXT: blr entry: %cmp = icmp sgt i32 %i, 0 %add = add nsw i32 %i, 1 %cond = select i1 %cmp, i32 %add, i32 %j ret i32 %cond -; CHECK-LABEL: @testExpandISELToIfElse -; CHECK: addi r5, r3, 1 -; CHECK-NEXT: cmpwi r3, 0 -; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] -; CHECK: ori r3, r4, 0 -; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: addi r3, r5, 0 -; CHECK-NEXT: [[SUCCESSOR]] -; CHECK-NEXT: extsw r3, r3 -; CHECK-NEXT: blr } - define signext i32 @testExpandISELToIf(i32 signext %i, i32 signext %j) { +; CHECK-LABEL: testExpandISELToIf: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpwi r3, 0 +; CHECK-NEXT: bgt cr0, .LBB1_2 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: mr r4, r3 +; CHECK-NEXT: .LBB1_2: # %entry +; CHECK-NEXT: mr r3, r4 +; CHECK-NEXT: blr entry: %cmp = icmp sgt i32 %i, 0 %cond = select i1 %cmp, i32 %j, i32 %i ret i32 %cond -; CHECK-LABEL: @testExpandISELToIf -; CHECK: cmpwi r3, 0 -; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] -; CHECK-NEXT: blr -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: addi r3, r4, 0 -; CHECK-NEXT: blr } define signext i32 @testExpandISELToElse(i32 signext %i, i32 signext %j) { +; CHECK-LABEL: testExpandISELToElse: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpwi r3, 0 +; CHECK-NEXT: bgtlr cr0 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: mr r3, r4 +; CHECK-NEXT: blr entry: %cmp = icmp sgt i32 %i, 0 %cond = select i1 %cmp, i32 %i, i32 %j ret i32 %cond -; CHECK-LABEL: @testExpandISELToElse -; CHECK: cmpwi r3, 0 -; CHECK-NEXT: bclr 12, gt, 0 -; CHECK: ori r3, r4, 0 -; CHECK-NEXT: blr } - define signext i32 @testExpandISELToNull(i32 signext %i, i32 signext %j) { +; CHECK-LABEL: testExpandISELToNull: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: blr entry: %cmp = icmp sgt i32 %i, 0 %cond = select i1 %cmp, i32 %i, i32 %i ret i32 %cond -; CHECK-LABEL: @testExpandISELToNull -; CHECK-NOT: b {{.LBB[0-9]+}} -; CHECK-NOT: bc -; CHECK: blr } -define signext i32 @testExpandISELsTo2ORIs2ADDIs - (i32 signext %a, i32 signext %b, i32 signext %d, - i32 signext %f, i32 signext %g) { +define signext i32 @testExpandISELsTo2ORIs2ADDIs(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { +; CHECK-LABEL: testExpandISELsTo2ORIs2ADDIs: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpwi r7, 0 +; CHECK-NEXT: bgt cr0, .LBB4_2 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: mr r7, r4 +; CHECK-NEXT: .LBB4_2: # %entry +; CHECK-NEXT: bgt cr0, .LBB4_4 +; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: mr r5, r6 +; CHECK-NEXT: .LBB4_4: # %entry +; CHECK-NEXT: add r3, r7, r5 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: blr entry: - %cmp = icmp sgt i32 %g, 0 %a.b = select i1 %cmp, i32 %g, i32 %b %d.f = select i1 %cmp, i32 %d, i32 %f %add = add nsw i32 %a.b, %d.f ret i32 %add - -; CHECK-LABEL: @testExpandISELsTo2ORIs2ADDIs -; CHECK: cmpwi r7, 0 -; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] -; CHECK: ori r3, r4, 0 -; CHECK-NEXT: ori r4, r6, 0 -; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: addi r3, r7, 0 -; CHECK-NEXT: addi r4, r5, 0 -; CHECK-NEXT: [[SUCCESSOR]] -; CHECK-NEXT: add r3, r3, r4 -; CHECK-NEXT: extsw r3, r3 -; CHECK-NEXT: blr } -define signext i32 @testExpandISELsTo2ORIs1ADDI - (i32 signext %a, i32 signext %b, i32 signext %d, - i32 signext %f, i32 signext %g) { +define signext i32 @testExpandISELsTo2ORIs1ADDI(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { +; CHECK-LABEL: testExpandISELsTo2ORIs1ADDI: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpwi r7, 0 +; CHECK-NEXT: bgt cr0, .LBB5_2 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: mr r3, r4 +; CHECK-NEXT: .LBB5_2: # %entry +; CHECK-NEXT: bgt cr0, .LBB5_4 +; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: mr r5, r6 +; CHECK-NEXT: .LBB5_4: # %entry +; CHECK-NEXT: add r3, r3, r5 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: blr entry: %cmp = icmp sgt i32 %g, 0 %a.b = select i1 %cmp, i32 %a, i32 %b %d.f = select i1 %cmp, i32 %d, i32 %f %add = add nsw i32 %a.b, %d.f ret i32 %add - -; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI -; CHECK: cmpwi r7, 0 -; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] -; CHECK: ori r3, r4, 0 -; CHECK-NEXT: ori r4, r6, 0 -; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: addi r4, r5, 0 -; CHECK-NEXT: [[SUCCESSOR]] -; CHECK-NEXT: add r3, r3, r4 -; CHECK-NEXT: extsw r3, r3 -; CHECK-NEXT: blr } -define signext i32 @testExpandISELsTo1ORI1ADDI - (i32 signext %a, i32 signext %b, i32 signext %d, - i32 signext %f, i32 signext %g) { +define signext i32 @testExpandISELsTo1ORI1ADDI(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { +; CHECK-LABEL: testExpandISELsTo1ORI1ADDI: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpwi r7, 0 +; CHECK-NEXT: mr r7, r3 +; CHECK-NEXT: bgt cr0, .LBB6_2 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: mr r7, r4 +; CHECK-NEXT: .LBB6_2: # %entry +; CHECK-NEXT: bgt cr0, .LBB6_4 +; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: mr r5, r6 +; CHECK-NEXT: .LBB6_4: # %entry +; CHECK-NEXT: add r4, r7, r5 +; CHECK-NEXT: add r3, r3, r4 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: blr entry: - %cmp = icmp sgt i32 %g, 0 %a.b = select i1 %cmp, i32 %a, i32 %b %d.f = select i1 %cmp, i32 %d, i32 %f %add1 = add nsw i32 %a.b, %d.f %add2 = add nsw i32 %a, %add1 ret i32 %add2 - -; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI -; CHECK: cmpwi r7, 0 -; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] -; CHECK: ori r5, r6, 0 -; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: addi r4, r3, 0 -; CHECK-NEXT: [[SUCCESSOR]] -; CHECK-NEXT: add r4, r4, r5 -; CHECK-NEXT: add r3, r3, r4 -; CHECK-NEXT: extsw r3, r3 -; CHECK-NEXT: blr } -define signext i32 @testExpandISELsTo0ORI2ADDIs - (i32 signext %a, i32 signext %b, i32 signext %d, - i32 signext %f, i32 signext %g) { +define signext i32 @testExpandISELsTo0ORI2ADDIs(i32 signext %a, i32 signext %b, i32 signext %d, i32 signext %f, i32 signext %g) { +; CHECK-LABEL: testExpandISELsTo0ORI2ADDIs: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpwi r7, 0 +; CHECK-NEXT: mr r7, r3 +; CHECK-NEXT: bgt cr0, .LBB7_2 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: mr r7, r4 +; CHECK-NEXT: .LBB7_2: # %entry +; CHECK-NEXT: mr r4, r5 +; CHECK-NEXT: bgt cr0, .LBB7_4 +; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: mr r4, r6 +; CHECK-NEXT: .LBB7_4: # %entry +; CHECK-NEXT: add r4, r7, r4 +; CHECK-NEXT: add r3, r3, r4 +; CHECK-NEXT: sub r3, r3, r5 +; CHECK-NEXT: extsw r3, r3 +; CHECK-NEXT: blr entry: - %cmp = icmp sgt i32 %g, 0 %a.b = select i1 %cmp, i32 %a, i32 %b %d.f = select i1 %cmp, i32 %d, i32 %f @@ -152,27 +163,30 @@ entry: %add2 = add nsw i32 %a, %add1 %sub1 = sub nsw i32 %add2, %d ret i32 %sub1 - -; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs -; CHECK: cmpwi r7, 0 -; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] -; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NEXT: [[TRUE]] -; CHECK-NEXT: addi r4, r3, 0 -; CHECK-NEXT: addi r6, r5, 0 -; CHECK-NEXT: [[SUCCESSOR]] -; CHECK-NEXT: add r4, r4, r6 -; CHECK-NEXT: add r3, r3, r4 -; CHECK-NEXT: sub r3, r3, r5 -; CHECK-NEXT: extsw r3, r3 -; CHECK-NEXT: blr } - @b = local_unnamed_addr global i32 0, align 4 @a = local_unnamed_addr global i32 0, align 4 ; Function Attrs: norecurse nounwind readonly define signext i32 @testComplexISEL() #0 { +; CHECK-LABEL: testComplexISEL: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r3, r2, .LC0@toc@ha +; CHECK-NEXT: ld r3, .LC0@toc@l(r3) +; CHECK-NEXT: lwz r4, 0(r3) +; CHECK-NEXT: li r3, 1 +; CHECK-NEXT: cmplwi r4, 0 +; CHECK-NEXT: bnelr cr0 +; CHECK-NEXT: # %bb.1: # %if.end +; CHECK-NEXT: addis r3, r2, .LC1@toc@ha +; CHECK-NEXT: addis r4, r2, .LC2@toc@ha +; CHECK-NEXT: ld r3, .LC1@toc@l(r3) +; CHECK-NEXT: ld r4, .LC2@toc@l(r4) +; CHECK-NEXT: lwa r3, 0(r3) +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 +; CHECK-NEXT: blr entry: %0 = load i32, ptr @b, align 4, !tbaa !1 %tobool = icmp eq i32 %0, 0 @@ -190,13 +204,6 @@ cleanup: %retval.0 = phi i32 [ %conv3, %if.end ], [ 1, %entry ] ret i32 %retval.0 -; CHECK-LABEL: @testComplexISEL -; CHECK: li r3, 1 -; CHECK: cmplwi r4, 0 -; CHECK: bnelr cr0 -; CHECK: xor [[XOR:r[0-9]+]] -; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]] -; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63 } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/PowerPC/fold-zero.ll b/llvm/test/CodeGen/PowerPC/fold-zero.ll index 6262d24040a3..a071464ac641 100644 --- a/llvm/test/CodeGen/PowerPC/fold-zero.ll +++ b/llvm/test/CodeGen/PowerPC/fold-zero.ll @@ -1,40 +1,62 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-CRB %s -; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mattr=-isel < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" define i32 @test1(i1 %a, i32 %c) nounwind { +; CHECK-LABEL: test1: +; CHECK: # %bb.0: +; CHECK-NEXT: andi. 3, 3, 1 +; CHECK-NEXT: iseleq 3, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-CRB-LABEL: test1: +; CHECK-CRB: # %bb.0: +; CHECK-CRB-NEXT: andi. 3, 3, 1 +; CHECK-CRB-NEXT: li 3, 0 +; CHECK-CRB-NEXT: iselgt 3, 4, 3 +; CHECK-CRB-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: test1: +; CHECK-NO-ISEL: # %bb.0: +; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1 +; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: +; CHECK-NO-ISEL-NEXT: li 4, 0 +; CHECK-NO-ISEL-NEXT: .LBB0_2: +; CHECK-NO-ISEL-NEXT: mr 3, 4 +; CHECK-NO-ISEL-NEXT: blr %x = select i1 %a, i32 %c, i32 0 ret i32 %x -; CHECK-LABEL: @test1 -; CHECK-NOT: li {{[0-9]+}}, 0 -; CHECK: iseleq 3, 0, -; CHECK: blr -; CHECK-NO-ISEL-LABEL: @test1 -; CHECK-NO-ISEL: li 3, 0 -; CHECK-NO-ISEL-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: [[TRUE]] -; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 -; CHECK-NO-ISEL-NEXT: blr } define i32 @test2(i1 %a, i32 %c) nounwind { +; CHECK-LABEL: test2: +; CHECK: # %bb.0: +; CHECK-NEXT: andi. 3, 3, 1 +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: iseleq 3, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-CRB-LABEL: test2: +; CHECK-CRB: # %bb.0: +; CHECK-CRB-NEXT: andi. 3, 3, 1 +; CHECK-CRB-NEXT: iselgt 3, 0, 4 +; CHECK-CRB-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: test2: +; CHECK-NO-ISEL: # %bb.0: +; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1 +; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: bclr 12, 1, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: +; CHECK-NO-ISEL-NEXT: mr 3, 4 +; CHECK-NO-ISEL-NEXT: blr %x = select i1 %a, i32 0, i32 %c ret i32 %x -; CHECK-CRB-LABEL: @test2 -; CHECK-CRB-NOT: li {{[0-9]+}}, 0 -; CHECK-CRB: iselgt 3, 0, -; CHECK-CRB: blr -; CHECK-NO-ISEL-LABEL: @test2 -; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 3, 4, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: [[TRUE]] -; CHECK-NO-ISEL-NEXT: li 3, 0 -; CHECK-NO-ISEL-NEXT: blr } diff --git a/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll b/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll index 0a666860cbd7..a1be8d39994d 100644 --- a/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll +++ b/llvm/test/CodeGen/PowerPC/i1-ext-fold.ll @@ -1,32 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind readnone define signext i32 @foo(i32 signext %a, i32 signext %b) #0 { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpw 3, 4 +; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: li 4, 16 +; CHECK-NEXT: isellt 3, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: foo: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: li 3, 16 +; CHECK-NO-ISEL-NEXT: bclr 12, 0, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: blr entry: %cmp = icmp slt i32 %a, %b %conv = zext i1 %cmp to i32 %shl = shl nuw nsw i32 %conv, 4 ret i32 %shl -; CHECK-LABEL: @foo -; CHECK-NO-ISEL-LABEL: @foo -; CHECK-DAG: cmpw -; CHECK-DAG: li [[REG1:[0-9]+]], 0 -; CHECK-DAG: li [[REG2:[0-9]+]], 16 -; CHECK: isellt 3, [[REG2]], [[REG1]] -; CHECK: blr -; CHECK-NO-ISEL: bc 12, 0, -; CHECK-NO-ISEL: blr -; CHECK-NO-ISEL: addi 3, 4, 0 -; CHECK-NO-ISEL-NEXT: blr } ; Function Attrs: nounwind readnone define signext i32 @foo2(i32 signext %a, i32 signext %b) #0 { +; CHECK-LABEL: foo2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpw 3, 4 +; CHECK-NEXT: li 3, 5 +; CHECK-NEXT: li 4, 21 +; CHECK-NEXT: isellt 3, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: foo2: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: li 3, 21 +; CHECK-NO-ISEL-NEXT: bclr 12, 0, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 5 +; CHECK-NO-ISEL-NEXT: blr entry: %cmp = icmp slt i32 %a, %b %conv = zext i1 %cmp to i32 @@ -34,40 +56,33 @@ entry: %add1 = or i32 %shl, 5 ret i32 %add1 -; CHECK-LABEL: @foo2 -; CHECK-NO-ISEL-LABEL: @foo2 -; CHECK-DAG: cmpw -; CHECK-DAG: li [[REG1:[0-9]+]], 5 -; CHECK-DAG: li [[REG2:[0-9]+]], 21 -; CHECK: isellt 3, [[REG2]], [[REG1]] -; CHECK: blr -; CHECK-NO-ISEL: bc 12, 0, -; CHECK-NO-ISEL: blr -; CHECK-NO-ISEL: addi 3, 4, 0 -; CHECK-NO-ISEL-NEXT: blr } ; Function Attrs: nounwind readnone define signext i32 @foo3(i32 signext %a, i32 signext %b) #0 { +; CHECK-LABEL: foo3: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpw 3, 4 +; CHECK-NEXT: li 3, 16 +; CHECK-NEXT: iselgt 3, 0, 3 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: foo3: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: bclr 12, 1, 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 16 +; CHECK-NO-ISEL-NEXT: blr entry: %cmp = icmp sle i32 %a, %b %conv = zext i1 %cmp to i32 %shl = shl nuw nsw i32 %conv, 4 ret i32 %shl -; CHECK-LABEL: @foo3 -; CHECK-NO-ISEL-LABEL: @foo3 -; CHECK-DAG: cmpw -; CHECK-DAG: li [[REG1:[0-9]+]], 16 -; CHECK: iselgt 3, 0, [[REG1]] -; CHECK: blr -; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: [[TRUE]] -; CHECK-NO-ISEL-NEXT: li 3, 0 -; CHECK-NO-ISEL-NEXT: blr } attributes #0 = { nounwind readnone } diff --git a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll index 340d9aff8f85..f7df003fcc3f 100644 --- a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll +++ b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll @@ -1,37 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; Verify that we get the code sequence needed to avoid double-rounding. +; Note that only parts of the sequence are checked for here, to allow +; for minor code generation differences. ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -ppc-gen-isel=false < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -mattr=-isel < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL +; Also check that with -enable-unsafe-fp-math we do not get that extra +; code sequence. Simply verify that there is no "isel" present. +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE +; CHECK-UNSAFE-NOT: isel target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" define float @test(i64 %x) nounwind readnone { -entry: - %conv = sitofp i64 %x to float - ret float %conv -} - ; Verify that we get the code sequence needed to avoid double-rounding. ; Note that only parts of the sequence are checked for here, to allow ; for minor code generation differences. - -;CHECK-LABEL: test -;CHECK-NO-ISEL-LABEL: test -; CHECK: sradi [[REG1:[0-9]+]], 3, 53 -; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1 -; CHECK: cmpldi [[REG2]], 1 -; CHECK: iselgt [[REG3:[0-9]+]], {{[0-9]+}}, 3 -; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52 -; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NO-ISEL-NEXT: [[TRUE]] -; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, [[REG2]], 0 -; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]] -; CHECK-NO-ISEL: std {{[0-9]+}}, -{{[0-9]+}}(1) -; CHECK: std [[REG3]], -{{[0-9]+}}(1) - - ; Also check that with -enable-unsafe-fp-math we do not get that extra ; code sequence. Simply verify that there is no "isel" present. - ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE -; CHECK-UNSAFE-NOT: isel +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: clrldi 4, 3, 53 +; CHECK-NEXT: sradi 5, 3, 53 +; CHECK-NEXT: addi 4, 4, 2047 +; CHECK-NEXT: addi 5, 5, 1 +; CHECK-NEXT: or 4, 4, 3 +; CHECK-NEXT: cmpldi 5, 1 +; CHECK-NEXT: rldicr 4, 4, 0, 52 +; CHECK-NEXT: iselgt 3, 4, 3 +; CHECK-NEXT: std 3, -8(1) +; CHECK-NEXT: lfd 0, -8(1) +; CHECK-NEXT: xscvsxddp 0, 0 +; CHECK-NEXT: frsp 1, 0 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: test: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: sradi 4, 3, 53 +; CHECK-NO-ISEL-NEXT: addi 4, 4, 1 +; CHECK-NO-ISEL-NEXT: cmpldi 4, 1 +; CHECK-NO-ISEL-NEXT: bc 4, 1, .LBB0_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: +; CHECK-NO-ISEL-NEXT: clrldi 4, 3, 53 +; CHECK-NO-ISEL-NEXT: addi 4, 4, 2047 +; CHECK-NO-ISEL-NEXT: or 3, 4, 3 +; CHECK-NO-ISEL-NEXT: rldicr 3, 3, 0, 52 +; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry +; CHECK-NO-ISEL-NEXT: std 3, -8(1) +; CHECK-NO-ISEL-NEXT: lfd 0, -8(1) +; CHECK-NO-ISEL-NEXT: xscvsxddp 0, 0 +; CHECK-NO-ISEL-NEXT: frsp 1, 0 +; CHECK-NO-ISEL-NEXT: blr +; +; CHECK-UNSAFE-LABEL: test: +; CHECK-UNSAFE: # %bb.0: # %entry +; CHECK-UNSAFE-NEXT: std 3, -8(1) +; CHECK-UNSAFE-NEXT: lfd 0, -8(1) +; CHECK-UNSAFE-NEXT: xscvsxddp 0, 0 +; CHECK-UNSAFE-NEXT: frsp 1, 0 +; CHECK-UNSAFE-NEXT: blr + +entry: + %conv = sitofp i64 %x to float + ret float %conv +} + diff --git a/llvm/test/CodeGen/PowerPC/ifcvt.ll b/llvm/test/CodeGen/PowerPC/ifcvt.ll index f04deb37a575..6b9d872f4aad 100644 --- a/llvm/test/CodeGen/PowerPC/ifcvt.ll +++ b/llvm/test/CodeGen/PowerPC/ifcvt.ll @@ -1,9 +1,41 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -mattr=-isel | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: slwi 5, 6, 16 +; CHECK-NEXT: extsh 6, 6 +; CHECK-NEXT: cmpwi 5, -1 +; CHECK-NEXT: add 5, 6, 3 +; CHECK-NEXT: clrlwi 6, 6, 17 +; CHECK-NEXT: sub 6, 3, 6 +; CHECK-NEXT: sub 3, 4, 3 +; CHECK-NEXT: iselgt 5, 5, 6 +; CHECK-NEXT: extsh 5, 5 +; CHECK-NEXT: add 3, 3, 5 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: test: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: slwi 7, 6, 16 +; CHECK-NO-ISEL-NEXT: extsh 5, 6 +; CHECK-NO-ISEL-NEXT: cmpwi 7, -1 +; CHECK-NO-ISEL-NEXT: ble 0, .LBB0_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %cond.false +; CHECK-NO-ISEL-NEXT: add 5, 5, 3 +; CHECK-NO-ISEL-NEXT: b .LBB0_3 +; CHECK-NO-ISEL-NEXT: .LBB0_2: # %cond.true +; CHECK-NO-ISEL-NEXT: clrlwi 5, 5, 17 +; CHECK-NO-ISEL-NEXT: sub 5, 3, 5 +; CHECK-NO-ISEL-NEXT: .LBB0_3: # %cond.end +; CHECK-NO-ISEL-NEXT: extsh 5, 5 +; CHECK-NO-ISEL-NEXT: sub 3, 4, 3 +; CHECK-NO-ISEL-NEXT: add 3, 3, 5 +; CHECK-NO-ISEL-NEXT: blr entry: %sext82 = shl i32 %d, 16 %conv29 = ashr exact i32 %sext82, 16 @@ -19,18 +51,6 @@ cond.false: ; preds = %sw.epilog %add37 = add nsw i32 %conv29, %a br label %cond.end -; CHECK-LABEL: @test -; CHECK-NO-ISEL-LABEL: @test -; CHECK: add [[REG:[0-9]+]], -; CHECK: sub [[REG2:[0-9]+]], -; CHECK: iselgt {{[0-9]+}}, [[REG]], [[REG2]] -; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 5, 6, 0 -; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NO-ISEL: [[TRUE]] -; CHECK-NO-ISEL: extsh 5, 5 -; CHECK-NO-ISEL-NEXT: add 3, 3, 5 -; CHECK-NO-ISEL-NEXT: blr cond.end: ; preds = %cond.false, %cond.true %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ] diff --git a/llvm/test/CodeGen/PowerPC/isel.ll b/llvm/test/CodeGen/PowerPC/isel.ll index c1cceb967018..5f64df5dfeb9 100644 --- a/llvm/test/CodeGen/PowerPC/isel.ll +++ b/llvm/test/CodeGen/PowerPC/isel.ll @@ -1,38 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" ; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) { +; CHECK-LABEL: test1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpld 3, 4 +; CHECK-NEXT: isellt 3, 6, 5 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: test1: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cmpld 3, 4 +; CHECK-NO-ISEL-NEXT: bge 0, .LBB0_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 5, 6 +; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 5 +; CHECK-NO-ISEL-NEXT: blr entry: %p = icmp uge i64 %a, %b %x = select i1 %p, i64 %c, i64 %d ret i64 %x -; CHECK-LABEL: @test1 -; CHECK-NO-ISEL-LABEL: @test1 -; CHECK: isel -; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 3, 5, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL: [[TRUE]] -; CHECK-NO-ISEL-NEXT: addi 3, 6, 0 -; CHECK-NO-ISEL-NEXT: blr } define i32 @test2(i32 %a, i32 %b, i32 %c, i32 %d) { +; CHECK-LABEL: test2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmplw 3, 4 +; CHECK-NEXT: isellt 3, 6, 5 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: test2: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cmplw 3, 4 +; CHECK-NO-ISEL-NEXT: bge 0, .LBB1_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 5, 6 +; CHECK-NO-ISEL-NEXT: .LBB1_2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 5 +; CHECK-NO-ISEL-NEXT: blr entry: %p = icmp uge i32 %a, %b %x = select i1 %p, i32 %c, i32 %d ret i32 %x -; CHECK-LABEL: @test2 -; CHECK-NO-ISEL-LABEL: @test2 -; CHECK: isel -; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 3, 5, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL: [[TRUE]] -; CHECK-NO-ISEL-NEXT: addi 3, 6, 0 -; CHECK-NO-ISEL-NEXT: blr } diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll index bc265c646d47..831bc97cc0e9 100644 --- a/llvm/test/CodeGen/PowerPC/optcmp.ll +++ b/llvm/test/CodeGen/PowerPC/optcmp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s -; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -mattr=-isel | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -16,14 +16,12 @@ define signext i32 @foo(i32 signext %a, i32 signext %b, ptr nocapture %c) #0 { ; ; CHECK-NO-ISEL-LABEL: foo: ; CHECK-NO-ISEL: # %bb.0: # %entry -; CHECK-NO-ISEL-NEXT: cmpw 3, 4 ; CHECK-NO-ISEL-NEXT: sub 6, 3, 4 -; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_2 -; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 -; CHECK-NO-ISEL-NEXT: b .LBB0_2 -; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 ; CHECK-NO-ISEL-NEXT: stw 6, 0(5) +; CHECK-NO-ISEL-NEXT: bgtlr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr entry: %sub = sub nsw i32 %a, %b @@ -46,14 +44,14 @@ define signext i32 @foo2(i32 signext %a, i32 signext %b, ptr nocapture %c) #0 { ; ; CHECK-NO-ISEL-LABEL: foo2: ; CHECK-NO-ISEL: # %bb.0: # %entry -; CHECK-NO-ISEL-NEXT: slw 4, 3, 4 -; CHECK-NO-ISEL-NEXT: li 6, 0 +; CHECK-NO-ISEL-NEXT: mr 6, 3 ; CHECK-NO-ISEL-NEXT: li 3, 1 +; CHECK-NO-ISEL-NEXT: slw 4, 6, 4 ; CHECK-NO-ISEL-NEXT: cmpwi 4, 0 ; CHECK-NO-ISEL-NEXT: stw 4, 0(5) -; CHECK-NO-ISEL-NEXT: bclr 12, 1, 0 +; CHECK-NO-ISEL-NEXT: bgtlr 0 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 6, 0 +; CHECK-NO-ISEL-NEXT: li 3, 0 ; CHECK-NO-ISEL-NEXT: blr entry: %shl = shl i32 %a, %b @@ -74,12 +72,10 @@ define i64 @fool(i64 %a, i64 %b, ptr nocapture %c) #0 { ; CHECK-NO-ISEL-LABEL: fool: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4 -; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB2_2 -; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 -; CHECK-NO-ISEL-NEXT: b .LBB2_2 -; CHECK-NO-ISEL-NEXT: .LBB2_2: # %entry ; CHECK-NO-ISEL-NEXT: std 6, 0(5) +; CHECK-NO-ISEL-NEXT: bgtlr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr entry: %sub = sub nsw i64 %a, %b @@ -100,12 +96,10 @@ define i64 @foolb(i64 %a, i64 %b, ptr nocapture %c) #0 { ; CHECK-NO-ISEL-LABEL: foolb: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4 -; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB3_1 -; CHECK-NO-ISEL-NEXT: b .LBB3_2 -; CHECK-NO-ISEL-NEXT: .LBB3_1: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 -; CHECK-NO-ISEL-NEXT: .LBB3_2: # %entry ; CHECK-NO-ISEL-NEXT: std 6, 0(5) +; CHECK-NO-ISEL-NEXT: blelr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr entry: %sub = sub nsw i64 %a, %b @@ -126,12 +120,10 @@ define i64 @foolc(i64 %a, i64 %b, ptr nocapture %c) #0 { ; CHECK-NO-ISEL-LABEL: foolc: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3 -; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB4_2 -; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 -; CHECK-NO-ISEL-NEXT: b .LBB4_2 -; CHECK-NO-ISEL-NEXT: .LBB4_2: # %entry ; CHECK-NO-ISEL-NEXT: std 6, 0(5) +; CHECK-NO-ISEL-NEXT: bltlr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr entry: %sub = sub nsw i64 %b, %a @@ -152,12 +144,10 @@ define i64 @foold(i64 %a, i64 %b, ptr nocapture %c) #0 { ; CHECK-NO-ISEL-LABEL: foold: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3 -; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB5_2 -; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 -; CHECK-NO-ISEL-NEXT: b .LBB5_2 -; CHECK-NO-ISEL-NEXT: .LBB5_2: # %entry ; CHECK-NO-ISEL-NEXT: std 6, 0(5) +; CHECK-NO-ISEL-NEXT: bgtlr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr entry: %sub = sub nsw i64 %b, %a @@ -178,12 +168,10 @@ define i64 @foold2(i64 %a, i64 %b, ptr nocapture %c) #0 { ; CHECK-NO-ISEL-LABEL: foold2: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4 -; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB6_2 -; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 -; CHECK-NO-ISEL-NEXT: b .LBB6_2 -; CHECK-NO-ISEL-NEXT: .LBB6_2: # %entry ; CHECK-NO-ISEL-NEXT: std 6, 0(5) +; CHECK-NO-ISEL-NEXT: bltlr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr entry: %sub = sub nsw i64 %a, %b @@ -336,12 +324,10 @@ define signext i64 @fooct(i64 signext %a, i64 signext %b, ptr nocapture %c) #0 { ; CHECK-NO-ISEL-NEXT: and 6, 6, 7 ; CHECK-NO-ISEL-NEXT: mulld 6, 6, 9 ; CHECK-NO-ISEL-NEXT: rldicl. 6, 6, 8, 56 -; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB10_2 -; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 -; CHECK-NO-ISEL-NEXT: b .LBB10_2 -; CHECK-NO-ISEL-NEXT: .LBB10_2: # %entry ; CHECK-NO-ISEL-NEXT: std 6, 0(5) +; CHECK-NO-ISEL-NEXT: bgtlr 0 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 4 ; CHECK-NO-ISEL-NEXT: blr entry: %sub = sub nsw i64 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll b/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll index 7e2515ff7093..cde5870db394 100644 --- a/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll +++ b/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll @@ -1,10 +1,62 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind define void @foo(ptr nocapture %r1, ptr nocapture %r2, ptr nocapture %r3, ptr nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 { +; Make sure that we don't schedule all of the isels together, they should be +; intermixed with the adds because each isel starts a new dispatch group. +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmplwi 7, 0 +; CHECK-NEXT: addi 7, 8, 1 +; CHECK-NEXT: iseleq 9, 9, 8 +; CHECK-NEXT: stw 9, 0(3) +; CHECK-NEXT: addi 3, 10, -2 +; CHECK-NEXT: iseleq 9, 10, 8 +; CHECK-NEXT: iseleq 3, 3, 7 +; CHECK-NEXT: stw 9, 0(4) +; CHECK-NEXT: addi 4, 10, -5 +; CHECK-NEXT: stw 3, 0(5) +; CHECK-NEXT: addi 3, 8, 3 +; CHECK-NEXT: iseleq 3, 4, 3 +; CHECK-NEXT: stw 3, 0(6) +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: foo: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cmplwi 7, 0 +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 9 +; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry +; CHECK-NO-ISEL-NEXT: stw 7, 0(3) +; CHECK-NO-ISEL-NEXT: mr 3, 8 +; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_4 +; CHECK-NO-ISEL-NEXT: # %bb.3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 10 +; CHECK-NO-ISEL-NEXT: .LBB0_4: # %entry +; CHECK-NO-ISEL-NEXT: stw 3, 0(4) +; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_7 +; CHECK-NO-ISEL-NEXT: # %bb.5: # %entry +; CHECK-NO-ISEL-NEXT: addi 3, 10, -2 +; CHECK-NO-ISEL-NEXT: stw 3, 0(5) +; CHECK-NO-ISEL-NEXT: beq 0, .LBB0_8 +; CHECK-NO-ISEL-NEXT: .LBB0_6: +; CHECK-NO-ISEL-NEXT: addi 3, 8, 3 +; CHECK-NO-ISEL-NEXT: stw 3, 0(6) +; CHECK-NO-ISEL-NEXT: blr +; CHECK-NO-ISEL-NEXT: .LBB0_7: +; CHECK-NO-ISEL-NEXT: addi 3, 8, 1 +; CHECK-NO-ISEL-NEXT: stw 3, 0(5) +; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_6 +; CHECK-NO-ISEL-NEXT: .LBB0_8: # %entry +; CHECK-NO-ISEL-NEXT: addi 3, 10, -5 +; CHECK-NO-ISEL-NEXT: stw 3, 0(6) +; CHECK-NO-ISEL-NEXT: blr entry: %tobool = icmp ne i32 %a, 0 %cond = select i1 %tobool, i32 %b, i32 %c @@ -22,21 +74,4 @@ entry: ret void } -; Make sure that we don't schedule all of the isels together, they should be -; intermixed with the adds because each isel starts a new dispatch group. -; CHECK-LABEL: @foo -; CHECK-NO-ISEL-LABEL: @foo -; CHECK: isel -; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NO-ISEL: [[TRUE]] -; CHECK-NO-ISEL: addi {{[0-9]+}}, {{[0-9]+}}, -2 -; CHECK: addi -; CHECK: isel -; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 3, 7, 0 -; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NO-ISEL: [[TRUE]] -; CHECK: blr - attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll b/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll index 3d8dcbd00d01..49a5687afe4c 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll @@ -1,10 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind readnone define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 { +; CHECK-LABEL: crbitsoff: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw 4, 4 +; CHECK-NEXT: cmplwi 3, 0 +; CHECK-NEXT: li 3, 1 +; CHECK-NEXT: iseleq 3, 0, 3 +; CHECK-NEXT: rlwinm 4, 4, 27, 5, 31 +; CHECK-NEXT: and 3, 3, 4 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: crbitsoff: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cmplwi 3, 0 +; CHECK-NO-ISEL-NEXT: li 3, 1 +; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_2 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry +; CHECK-NO-ISEL-NEXT: li 3, 0 +; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry +; CHECK-NO-ISEL-NEXT: cntlzw 4, 4 +; CHECK-NO-ISEL-NEXT: rlwinm 4, 4, 27, 5, 31 +; CHECK-NO-ISEL-NEXT: and 3, 3, 4 +; CHECK-NO-ISEL-NEXT: blr entry: %tobool = icmp ne i32 %v1, 0 %lnot = icmp eq i32 %v2, 0 @@ -12,21 +35,28 @@ entry: %and = zext i1 %and3 to i32 ret i32 %and -; CHECK-LABEL: @crbitsoff -; CHECK-NO-ISEL-LABEL: @crbitsoff -; CHECK-DAG: cmplwi 3, 0 -; CHECK-DAG: li [[REG2:[0-9]+]], 1 -; CHECK-DAG: cntlzw [[REG3:[0-9]+]], -; CHECK: iseleq [[REG4:[0-9]+]], 0, [[REG2]] -; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NO-ISEL: [[TRUE]] -; CHECK-NO-ISEL-NEXT: li 3, 0 -; CHECK: and 3, [[REG4]], [[REG3]] -; CHECK: blr } define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 { +; CHECK-LABEL: crbitson: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cntlzw 3, 3 +; CHECK-NEXT: cntlzw 4, 4 +; CHECK-NEXT: srwi 3, 3, 5 +; CHECK-NEXT: srwi 4, 4, 5 +; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: and 3, 3, 4 +; CHECK-NEXT: blr +; +; CHECK-NO-ISEL-LABEL: crbitson: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: cntlzw 3, 3 +; CHECK-NO-ISEL-NEXT: cntlzw 4, 4 +; CHECK-NO-ISEL-NEXT: srwi 3, 3, 5 +; CHECK-NO-ISEL-NEXT: srwi 4, 4, 5 +; CHECK-NO-ISEL-NEXT: xori 3, 3, 1 +; CHECK-NO-ISEL-NEXT: and 3, 3, 4 +; CHECK-NO-ISEL-NEXT: blr entry: %tobool = icmp ne i32 %v1, 0 %lnot = icmp eq i32 %v2, 0 @@ -34,15 +64,6 @@ entry: %and = zext i1 %and3 to i32 ret i32 %and -; CHECK-LABEL: @crbitson -; CHECK-NO-ISEL-LABEL: @crbitson -; CHECK-DAG: cntlzw [[REG1:[0-9]+]], 3 -; CHECK-DAG: cntlzw [[REG2:[0-9]+]], 4 -; CHECK: srwi [[REG3:[0-9]+]], [[REG1]], 5 -; CHECK: srwi [[REG4:[0-9]+]], [[REG2]], 5 -; CHECK: xori [[REG5:[0-9]+]], [[REG3]], 1 -; CHECK: and 3, [[REG5]], [[REG4]] -; CHECK-NEXT: blr } diff --git a/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir b/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir index 28faace49117..f5b931e1e423 100644 --- a/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir +++ b/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir @@ -1,5 +1,5 @@ # RUN: llc -mtriple=powerpc64le-unknown-unknown -start-after=ppc-mi-peepholes \ -# RUN: -stop-before=ppc-expand-isel -verify-machineinstrs %s -o - | FileCheck %s +# RUN: -stop-after=ppc-pre-emit-peephole -verify-machineinstrs %s -o - | FileCheck %s --- | ; ModuleID = 'a.ll' source_filename = "a.c" diff --git a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll index d5e77a5cda06..ebf4cbcaac94 100644 --- a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll +++ b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs -tail-dup-placement=false < %s | FileCheck %s ; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs \ -; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -21,14 +21,16 @@ define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32slt: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB0_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB0_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB0_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -51,14 +53,16 @@ define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32ult: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB1_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB1_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB1_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB1_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -81,14 +85,14 @@ define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32sle: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB2_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB2_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB2_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB2_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -111,14 +115,14 @@ define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32ule: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB3_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB3_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB3_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB3_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB3_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -145,10 +149,9 @@ define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, ; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2 ; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB4_2 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr +; CHECK-NO-ISEL-NEXT: mr 7, 8 ; CHECK-NO-ISEL-NEXT: .LBB4_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -171,14 +174,14 @@ define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32sge: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB5_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB5_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB5_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB5_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB5_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -201,14 +204,14 @@ define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32uge: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB6_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB6_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB6_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB6_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB6_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -231,14 +234,16 @@ define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32sgt: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB7_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB7_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB7_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB7_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB7_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -261,14 +266,16 @@ define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3 ; CHECK-NO-ISEL-LABEL: testi32ugt: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpw 5, 6 -; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB8_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB8_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpw 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB8_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB8_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB8_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -295,10 +302,9 @@ define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, ; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2 ; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB9_2 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr +; CHECK-NO-ISEL-NEXT: mr 7, 8 ; CHECK-NO-ISEL-NEXT: .LBB9_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i32 %c3, %c4 @@ -321,14 +327,16 @@ define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64slt: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB10_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB10_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB10_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB10_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB10_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -351,14 +359,16 @@ define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64ult: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB11_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB11_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB11_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB11_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB11_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -381,14 +391,14 @@ define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64sle: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB12_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB12_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB12_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB12_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB12_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -411,14 +421,14 @@ define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64ule: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB13_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB13_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB13_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB13_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB13_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -445,10 +455,9 @@ define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { ; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2 ; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB14_2 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr +; CHECK-NO-ISEL-NEXT: mr 7, 8 ; CHECK-NO-ISEL-NEXT: .LBB14_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -471,14 +480,14 @@ define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64sge: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB15_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB15_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB15_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB15_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB15_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -501,14 +510,14 @@ define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64uge: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB16_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB16_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB16_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB16_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: .LBB16_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -531,14 +540,16 @@ define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64sgt: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB17_2 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB17_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB17_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB17_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB17_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -561,14 +572,16 @@ define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 ; CHECK-NO-ISEL-LABEL: testi64ugt: ; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL-NEXT: cmpd 5, 6 -; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4 -; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2 -; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB18_2 +; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB18_3 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 +; CHECK-NO-ISEL-NEXT: cmpd 3, 4 +; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB18_3 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr -; CHECK-NO-ISEL-NEXT: .LBB18_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: .LBB18_3: # %entry +; CHECK-NO-ISEL-NEXT: mr 7, 8 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 @@ -595,10 +608,9 @@ define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 { ; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2 ; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB19_2 ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry -; CHECK-NO-ISEL-NEXT: ori 3, 8, 0 -; CHECK-NO-ISEL-NEXT: blr +; CHECK-NO-ISEL-NEXT: mr 7, 8 ; CHECK-NO-ISEL-NEXT: .LBB19_2: # %entry -; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 +; CHECK-NO-ISEL-NEXT: mr 3, 7 ; CHECK-NO-ISEL-NEXT: blr entry: %cmp1 = icmp eq i64 %c3, %c4 diff --git a/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll b/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll index f952c0e2d8fb..f696745c9d41 100644 --- a/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll +++ b/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll @@ -1,10 +1,89 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gep-opt=0 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false -ppc-gep-opt=0 < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-isel -ppc-gep-opt=0 < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind define void @jbd2_journal_commit_transaction(i32 %input1, ptr %input2, ptr %input3, ptr %input4) #0 { +; CHECK-LABEL: jbd2_journal_commit_transaction: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi 7, 3, 1 +; CHECK-NEXT: cmplwi 1, 3, 0 +; CHECK-NEXT: li 8, -5 +; CHECK-NEXT: lis 9, 4 +; CHECK-NEXT: cmpld 6, 4, 5 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_1: # %while.body392 +; CHECK-NEXT: # +; CHECK-NEXT: bne- 1, .LBB0_4 +; CHECK-NEXT: # %bb.2: # %wait_on_buffer.exit1319 +; CHECK-NEXT: # +; CHECK-NEXT: ld 4, 0(6) +; CHECK-NEXT: mr 5, 4 +; CHECK-NEXT: ldu 10, -72(5) +; CHECK-NEXT: andi. 10, 10, 1 +; CHECK-NEXT: crmove 20, 1 +; CHECK-NEXT: #APP +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .long 2101356712 +; CHECK-NEXT: andc 10, 10, 9 +; CHECK-NEXT: stdcx. 10, 0, 5 +; CHECK-NEXT: bne- 0, .Ltmp0 +; CHECK-EMPTY: +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: std 4, 0(6) +; CHECK-NEXT: bne+ 6, .LBB0_1 +; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: isel 7, 3, 8, 20 +; CHECK-NEXT: .LBB0_4: # %while.end418 +; CHECK-NEXT: cmplwi 7, 0 +; CHECK-NEXT: beq 0, .LBB0_6 +; CHECK-NEXT: # %bb.5: # %if.then420 +; CHECK-NEXT: .LBB0_6: # %if.end421 +; +; CHECK-NO-ISEL-LABEL: jbd2_journal_commit_transaction: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: addi 7, 3, 1 +; CHECK-NO-ISEL-NEXT: cmplwi 1, 3, 0 +; CHECK-NO-ISEL-NEXT: lis 8, 4 +; CHECK-NO-ISEL-NEXT: cmpld 5, 4, 5 +; CHECK-NO-ISEL-NEXT: b .LBB0_2 +; CHECK-NO-ISEL-NEXT: .p2align 4 +; CHECK-NO-ISEL-NEXT: .LBB0_1: # %wait_on_buffer.exit1319 +; CHECK-NO-ISEL-NEXT: # +; CHECK-NO-ISEL-NEXT: #APP +; CHECK-NO-ISEL-NEXT: .Ltmp0: +; CHECK-NO-ISEL-NEXT: .long 2101364904 +; CHECK-NO-ISEL-NEXT: andc 10, 10, 8 +; CHECK-NO-ISEL-NEXT: stdcx. 10, 0, 9 +; CHECK-NO-ISEL-NEXT: bne- 0, .Ltmp0 +; CHECK-NO-ISEL-EMPTY: +; CHECK-NO-ISEL-NEXT: #NO_APP +; CHECK-NO-ISEL-NEXT: std 5, 0(6) +; CHECK-NO-ISEL-NEXT: beq- 5, .LBB0_6 +; CHECK-NO-ISEL-NEXT: .LBB0_2: # %while.body392 +; CHECK-NO-ISEL-NEXT: # +; CHECK-NO-ISEL-NEXT: bne- 1, .LBB0_5 +; CHECK-NO-ISEL-NEXT: # %bb.3: # %wait_on_buffer.exit1319 +; CHECK-NO-ISEL-NEXT: # +; CHECK-NO-ISEL-NEXT: ld 5, 0(6) +; CHECK-NO-ISEL-NEXT: mr 9, 5 +; CHECK-NO-ISEL-NEXT: ldu 4, -72(9) +; CHECK-NO-ISEL-NEXT: andi. 4, 4, 1 +; CHECK-NO-ISEL-NEXT: mr 4, 3 +; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_1 +; CHECK-NO-ISEL-NEXT: # %bb.4: # %wait_on_buffer.exit1319 +; CHECK-NO-ISEL-NEXT: # +; CHECK-NO-ISEL-NEXT: li 4, -5 +; CHECK-NO-ISEL-NEXT: b .LBB0_1 +; CHECK-NO-ISEL-NEXT: .LBB0_5: +; CHECK-NO-ISEL-NEXT: mr 4, 7 +; CHECK-NO-ISEL-NEXT: .LBB0_6: # %while.end418 +; CHECK-NO-ISEL-NEXT: cmplwi 4, 0 +; CHECK-NO-ISEL-NEXT: beq 0, .LBB0_8 +; CHECK-NO-ISEL-NEXT: # %bb.7: # %if.then420 +; CHECK-NO-ISEL-NEXT: .LBB0_8: # %if.end421 entry: br label %while.body392 @@ -30,17 +109,6 @@ while.end418: ; preds = %wait_on_buffer.exit %tobool419 = icmp eq i32 %err.4.lcssa, 0 br i1 %tobool419, label %if.end421, label %if.then420 -; CHECK-LABEL: @jbd2_journal_commit_transaction -; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction -; CHECK: andi. -; CHECK: crmove [[REG:[0-9]+]], 1 -; CHECK: stdcx. -; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]] -; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 7, 8, 0 -; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] -; CHECK-NO-ISEL: [[TRUE]] -; CHECK-NO-ISEL: addi 7, 3, 0 if.then420: ; preds = %while.end418 unreachable diff --git a/llvm/test/CodeGen/PowerPC/subreg-postra.ll b/llvm/test/CodeGen/PowerPC/subreg-postra.ll index 32a1b85cac8f..a315da545ba0 100644 --- a/llvm/test/CodeGen/PowerPC/subreg-postra.ll +++ b/llvm/test/CodeGen/PowerPC/subreg-postra.ll @@ -1,10 +1,232 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind define void @jbd2_journal_commit_transaction(ptr %journal, i64 %inp1, i32 %inp2, +; CHECK-LABEL: jbd2_journal_commit_transaction: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mfcr 12 +; CHECK-NEXT: mflr 0 +; CHECK-NEXT: stw 12, 8(1) +; CHECK-NEXT: stdu 1, -176(1) +; CHECK-NEXT: lbz 6, 295(1) +; CHECK-NEXT: std 0, 192(1) +; CHECK-NEXT: andi. 6, 6, 1 +; CHECK-NEXT: std 25, 120(1) # 8-byte Folded Spill +; CHECK-NEXT: std 26, 128(1) # 8-byte Folded Spill +; CHECK-NEXT: std 27, 136(1) # 8-byte Folded Spill +; CHECK-NEXT: std 28, 144(1) # 8-byte Folded Spill +; CHECK-NEXT: std 29, 152(1) # 8-byte Folded Spill +; CHECK-NEXT: std 30, 160(1) # 8-byte Folded Spill +; CHECK-NEXT: crmove 9, 1 +; CHECK-NEXT: andi. 6, 10, 1 +; CHECK-NEXT: crmove 8, 1 +; CHECK-NEXT: andi. 6, 9, 1 +; CHECK-NEXT: bc 4, 20, .LBB0_24 +; CHECK-NEXT: # %bb.1: # %do.body +; CHECK-NEXT: bc 4, 20, .LBB0_25 +; CHECK-NEXT: # %bb.2: # %trace_jbd2_start_commit.exit +; CHECK-NEXT: mr 30, 8 +; CHECK-NEXT: mr 29, 7 +; CHECK-NEXT: bc 12, 20, .LBB0_4 +; CHECK-NEXT: # %bb.3: # %do.body.i1116 +; CHECK-NEXT: bc 4, 20, .LBB0_26 +; CHECK-NEXT: .LBB0_4: # %trace_jbd2_commit_locking.exit +; CHECK-NEXT: bc 4, 20, .LBB0_27 +; CHECK-NEXT: # %bb.5: # %spin_unlock.exit1146 +; CHECK-NEXT: bc 4, 20, .LBB0_28 +; CHECK-NEXT: # %bb.6: # %trace_jbd2_commit_flushing.exit +; CHECK-NEXT: bc 4, 20, .LBB0_29 +; CHECK-NEXT: # %bb.7: # %for.end.i +; CHECK-NEXT: bc 4, 20, .LBB0_31 +; CHECK-NEXT: # %bb.8: # %journal_submit_data_buffers.exit +; CHECK-NEXT: bc 4, 20, .LBB0_32 +; CHECK-NEXT: # %bb.9: # %if.end103 +; CHECK-NEXT: bc 4, 20, .LBB0_33 +; CHECK-NEXT: # %bb.10: # %trace_jbd2_commit_logging.exit +; CHECK-NEXT: bc 4, 20, .LBB0_34 +; CHECK-NEXT: # %bb.11: # %for.end.i1287 +; CHECK-NEXT: bc 4, 20, .LBB0_35 +; CHECK-NEXT: # %bb.12: # %journal_finish_inode_data_buffers.exit +; CHECK-NEXT: bc 4, 20, .LBB0_36 +; CHECK-NEXT: # %bb.13: # %if.end256 +; CHECK-NEXT: cmpdi 1, 4, 0 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_14: # %while.body318 +; CHECK-NEXT: # +; CHECK-NEXT: bc 4, 6, .LBB0_19 +; CHECK-NEXT: # %bb.15: # %wait_on_buffer.exit +; CHECK-NEXT: # +; CHECK-NEXT: bc 4, 1, .LBB0_14 +; CHECK-NEXT: # %bb.16: # %do.body378 +; CHECK-NEXT: bc 4, 8, .LBB0_20 +; CHECK-NEXT: # %bb.17: # %while.end418 +; CHECK-NEXT: bc 4, 8, .LBB0_23 +; CHECK-NEXT: .LBB0_18: # %if.end421 +; CHECK-NEXT: .LBB0_19: # %if.then.i1296 +; CHECK-NEXT: .LBB0_20: # %while.body392.lr.ph +; CHECK-NEXT: lis 26, 4 +; CHECK-NEXT: mr 27, 5 +; CHECK-NEXT: mr 28, 3 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_21: # %while.body392 +; CHECK-NEXT: # +; CHECK-NEXT: ld 3, 0(3) +; CHECK-NEXT: ldu 25, -72(3) +; CHECK-NEXT: #APP +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .long 2088769704 +; CHECK-NEXT: andc 4, 4, 26 +; CHECK-NEXT: stdcx. 4, 0, 3 +; CHECK-NEXT: bne- 0, .Ltmp0 +; CHECK-EMPTY: +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: ld 3, 0(29) +; CHECK-NEXT: std 3, 0(30) +; CHECK-NEXT: bl __brelse +; CHECK-NEXT: nop +; CHECK-NEXT: bc 4, 9, .LBB0_21 +; CHECK-NEXT: # %bb.22: # %while.end418.loopexit +; CHECK-NEXT: andi. 3, 25, 1 +; CHECK-NEXT: li 3, -5 +; CHECK-NEXT: mr 5, 27 +; CHECK-NEXT: iselgt 5, 5, 3 +; CHECK-NEXT: mr 3, 28 +; CHECK-NEXT: bc 12, 8, .LBB0_18 +; CHECK-NEXT: .LBB0_23: # %if.then420 +; CHECK-NEXT: extsw 4, 5 +; CHECK-NEXT: bl jbd2_journal_abort +; CHECK-NEXT: nop +; CHECK-NEXT: .LBB0_24: # %if.then5 +; CHECK-NEXT: .LBB0_25: # %do.body.i +; CHECK-NEXT: .LBB0_26: # %do.body5.i1122 +; CHECK-NEXT: .LBB0_27: # %if.then.i.i.i.i1144 +; CHECK-NEXT: .LBB0_28: # %do.body.i1159 +; CHECK-NEXT: .LBB0_29: # %for.body.lr.ph.i +; CHECK-NEXT: bc 4, 20, .LBB0_37 +; CHECK-NEXT: # %bb.30: # %spin_unlock.exit.i +; CHECK-NEXT: .LBB0_31: # %if.then.i.i.i.i31.i +; CHECK-NEXT: .LBB0_32: # %if.then102 +; CHECK-NEXT: .LBB0_33: # %do.body.i1182 +; CHECK-NEXT: .LBB0_34: # %for.body.i1277 +; CHECK-NEXT: .LBB0_35: # %if.then.i.i.i.i84.i +; CHECK-NEXT: .LBB0_36: # %if.then249 +; CHECK-NEXT: .LBB0_37: # %if.then.i.i.i.i.i +; +; CHECK-NO-ISEL-LABEL: jbd2_journal_commit_transaction: +; CHECK-NO-ISEL: # %bb.0: # %entry +; CHECK-NO-ISEL-NEXT: mfcr 12 +; CHECK-NO-ISEL-NEXT: mflr 0 +; CHECK-NO-ISEL-NEXT: stw 12, 8(1) +; CHECK-NO-ISEL-NEXT: stdu 1, -176(1) +; CHECK-NO-ISEL-NEXT: lbz 6, 295(1) +; CHECK-NO-ISEL-NEXT: std 0, 192(1) +; CHECK-NO-ISEL-NEXT: andi. 6, 6, 1 +; CHECK-NO-ISEL-NEXT: std 25, 120(1) # 8-byte Folded Spill +; CHECK-NO-ISEL-NEXT: std 26, 128(1) # 8-byte Folded Spill +; CHECK-NO-ISEL-NEXT: std 27, 136(1) # 8-byte Folded Spill +; CHECK-NO-ISEL-NEXT: std 28, 144(1) # 8-byte Folded Spill +; CHECK-NO-ISEL-NEXT: std 29, 152(1) # 8-byte Folded Spill +; CHECK-NO-ISEL-NEXT: std 30, 160(1) # 8-byte Folded Spill +; CHECK-NO-ISEL-NEXT: crmove 9, 1 +; CHECK-NO-ISEL-NEXT: andi. 6, 10, 1 +; CHECK-NO-ISEL-NEXT: crmove 8, 1 +; CHECK-NO-ISEL-NEXT: andi. 6, 9, 1 +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_26 +; CHECK-NO-ISEL-NEXT: # %bb.1: # %do.body +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_27 +; CHECK-NO-ISEL-NEXT: # %bb.2: # %trace_jbd2_start_commit.exit +; CHECK-NO-ISEL-NEXT: mr 30, 8 +; CHECK-NO-ISEL-NEXT: mr 29, 7 +; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_4 +; CHECK-NO-ISEL-NEXT: # %bb.3: # %do.body.i1116 +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_28 +; CHECK-NO-ISEL-NEXT: .LBB0_4: # %trace_jbd2_commit_locking.exit +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_29 +; CHECK-NO-ISEL-NEXT: # %bb.5: # %spin_unlock.exit1146 +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_30 +; CHECK-NO-ISEL-NEXT: # %bb.6: # %trace_jbd2_commit_flushing.exit +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_31 +; CHECK-NO-ISEL-NEXT: # %bb.7: # %for.end.i +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_33 +; CHECK-NO-ISEL-NEXT: # %bb.8: # %journal_submit_data_buffers.exit +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_34 +; CHECK-NO-ISEL-NEXT: # %bb.9: # %if.end103 +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_35 +; CHECK-NO-ISEL-NEXT: # %bb.10: # %trace_jbd2_commit_logging.exit +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_36 +; CHECK-NO-ISEL-NEXT: # %bb.11: # %for.end.i1287 +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_37 +; CHECK-NO-ISEL-NEXT: # %bb.12: # %journal_finish_inode_data_buffers.exit +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_38 +; CHECK-NO-ISEL-NEXT: # %bb.13: # %if.end256 +; CHECK-NO-ISEL-NEXT: cmpdi 1, 4, 0 +; CHECK-NO-ISEL-NEXT: .p2align 4 +; CHECK-NO-ISEL-NEXT: .LBB0_14: # %while.body318 +; CHECK-NO-ISEL-NEXT: # +; CHECK-NO-ISEL-NEXT: bc 4, 6, .LBB0_19 +; CHECK-NO-ISEL-NEXT: # %bb.15: # %wait_on_buffer.exit +; CHECK-NO-ISEL-NEXT: # +; CHECK-NO-ISEL-NEXT: bc 4, 1, .LBB0_14 +; CHECK-NO-ISEL-NEXT: # %bb.16: # %do.body378 +; CHECK-NO-ISEL-NEXT: bc 4, 8, .LBB0_20 +; CHECK-NO-ISEL-NEXT: # %bb.17: # %while.end418 +; CHECK-NO-ISEL-NEXT: bc 4, 8, .LBB0_25 +; CHECK-NO-ISEL-NEXT: .LBB0_18: # %if.end421 +; CHECK-NO-ISEL-NEXT: .LBB0_19: # %if.then.i1296 +; CHECK-NO-ISEL-NEXT: .LBB0_20: # %while.body392.lr.ph +; CHECK-NO-ISEL-NEXT: lis 26, 4 +; CHECK-NO-ISEL-NEXT: mr 27, 5 +; CHECK-NO-ISEL-NEXT: mr 28, 3 +; CHECK-NO-ISEL-NEXT: .p2align 4 +; CHECK-NO-ISEL-NEXT: .LBB0_21: # %while.body392 +; CHECK-NO-ISEL-NEXT: # +; CHECK-NO-ISEL-NEXT: ld 3, 0(3) +; CHECK-NO-ISEL-NEXT: ldu 25, -72(3) +; CHECK-NO-ISEL-NEXT: #APP +; CHECK-NO-ISEL-NEXT: .Ltmp0: +; CHECK-NO-ISEL-NEXT: .long 2088769704 +; CHECK-NO-ISEL-NEXT: andc 4, 4, 26 +; CHECK-NO-ISEL-NEXT: stdcx. 4, 0, 3 +; CHECK-NO-ISEL-NEXT: bne- 0, .Ltmp0 +; CHECK-NO-ISEL-EMPTY: +; CHECK-NO-ISEL-NEXT: #NO_APP +; CHECK-NO-ISEL-NEXT: ld 3, 0(29) +; CHECK-NO-ISEL-NEXT: std 3, 0(30) +; CHECK-NO-ISEL-NEXT: bl __brelse +; CHECK-NO-ISEL-NEXT: nop +; CHECK-NO-ISEL-NEXT: bc 4, 9, .LBB0_21 +; CHECK-NO-ISEL-NEXT: # %bb.22: # %while.end418.loopexit +; CHECK-NO-ISEL-NEXT: andi. 3, 25, 1 +; CHECK-NO-ISEL-NEXT: mr 5, 27 +; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_24 +; CHECK-NO-ISEL-NEXT: # %bb.23: # %while.end418.loopexit +; CHECK-NO-ISEL-NEXT: li 5, -5 +; CHECK-NO-ISEL-NEXT: .LBB0_24: # %while.end418.loopexit +; CHECK-NO-ISEL-NEXT: mr 3, 28 +; CHECK-NO-ISEL-NEXT: bc 12, 8, .LBB0_18 +; CHECK-NO-ISEL-NEXT: .LBB0_25: # %if.then420 +; CHECK-NO-ISEL-NEXT: extsw 4, 5 +; CHECK-NO-ISEL-NEXT: bl jbd2_journal_abort +; CHECK-NO-ISEL-NEXT: nop +; CHECK-NO-ISEL-NEXT: .LBB0_26: # %if.then5 +; CHECK-NO-ISEL-NEXT: .LBB0_27: # %do.body.i +; CHECK-NO-ISEL-NEXT: .LBB0_28: # %do.body5.i1122 +; CHECK-NO-ISEL-NEXT: .LBB0_29: # %if.then.i.i.i.i1144 +; CHECK-NO-ISEL-NEXT: .LBB0_30: # %do.body.i1159 +; CHECK-NO-ISEL-NEXT: .LBB0_31: # %for.body.lr.ph.i +; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_39 +; CHECK-NO-ISEL-NEXT: # %bb.32: # %spin_unlock.exit.i +; CHECK-NO-ISEL-NEXT: .LBB0_33: # %if.then.i.i.i.i31.i +; CHECK-NO-ISEL-NEXT: .LBB0_34: # %if.then102 +; CHECK-NO-ISEL-NEXT: .LBB0_35: # %do.body.i1182 +; CHECK-NO-ISEL-NEXT: .LBB0_36: # %for.body.i1277 +; CHECK-NO-ISEL-NEXT: .LBB0_37: # %if.then.i.i.i.i84.i +; CHECK-NO-ISEL-NEXT: .LBB0_38: # %if.then249 +; CHECK-NO-ISEL-NEXT: .LBB0_39: # %if.then.i.i.i.i.i ptr %inp3, ptr %inp4, ptr %inp5, i1 %inp6, i1 %inp7, i1 %inp8) #0 { @@ -144,15 +366,6 @@ wait_on_buffer.exit1319: ; preds = %while.body392 call void @__brelse(ptr %3) #1 br i1 %inp8, label %while.end418, label %while.body392 -; CHECK-LABEL: @jbd2_journal_commit_transaction -; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction -; CHECK: andi. -; CHECK: crmove -; CHECK: stdcx. -; CHECK: iselgt {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} -; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]] -; CHECK-NO-ISEL: ori 5, 3, 0 -; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]] while.end418: ; preds = %wait_on_buffer.exit1319, %do.body378 |