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AgeCommit message (Expand)Author
2025-11-22LoongArch: extract the base address to promote the combine of RTX.zhaozhou
2025-11-22LoongArch: Optimize statement to use bstrins.{w|d}Deng Jianbo
2025-11-22LoongArch: Optimize V4SImode vec_construct for load index length of two.zhaozhou
2025-11-21aarch64: Extract aarch64_indirect_branch_asm for sibcall codegenKees Cook
2025-11-21i386: Remove cond_{ashl,lshr,ashr}v{64,16,32}qi expanders [PR122598]Jakub Jelinek
2025-11-21arc: emit clobber of CC for -mcpu=em x >> 31Loeka Rogge
2025-11-21arc: Use correct input operand for *extvsi_n_0 define_insn_and_splitClaudiu Zissulescu
2025-11-21LoongArch: Add more numbers supported for {x}vldiDeng Jianbo
2025-11-21LoongArch: Fix operands[2] predicate of lsx_vreplvei_mirror.zhaozhou
2025-11-20RISC-V: Add RTL pass to combine cm.popret with zero return valueKito Cheng
2025-11-20[PATCH v1] RISC-V: Fix missed zero extend for unsigned scalar SAT_TRUNC [PR12...Pan Li
2025-11-20Switch from USE_GAS/GLD to HAVE_GNU_AS/LDRainer Orth
2025-11-20driver: Simplify LINK_ARCH*_SPEC on SolarisRainer Orth
2025-11-20LoongArch: NFC: Drop loongarch_expand_vec_permXi Ruoyao
2025-11-20LoongArch: NFC: Simplify logic of vec_perm{v32qi,v16hi}Xi Ruoyao
2025-11-20LoongArch: Micro-optimize the blend step for vec_perm<LASX>Xi Ruoyao
2025-11-20LoongArch: NFC: Move [x]vshuf.* to simd.mdXi Ruoyao
2025-11-20LoongArch: NFC: Simplify vec_permv8sf logicXi Ruoyao
2025-11-20LoongArch: Avoid memory load when use xvperm.w for vec_permv4diXi Ruoyao
2025-11-20LoongArch: Fix wrong code from loongarch_expand_vec_perm_1 [PR 122695]Xi Ruoyao
2025-11-19aarch64: Fix ICE when laying out arguments of size 0 [PR 122763]Alfie Richards
2025-11-19AArch64: expand extractions of Adv.SIMD registers from SVE as separate insn.Tamar Christina
2025-11-19[RISC-V] Fix trivial bootstrap failure on RISC-VJeff Law
2025-11-19Fix typo in sol2.hRainer Orth
2025-11-19rs6000: Do not reorder operands for vec_pack_to_short_fp32 based on endiannessAvinash Jayakar
2025-11-19i386: Add AVX10.1, AVX10.2, APX_F and MOVRS to Nova LakeHaochen Jiang
2025-11-18RISC-V: Add flag to adjust mem inlining thresholdEdwin Lu
2025-11-18arm: [MVE intrinsics] remove __ARM_mve_typeid and __ARM_mve_coerce in arm_mve.hChristophe Lyon
2025-11-18arm: [MVE intrinsics] rework vuninitializedChristophe Lyon
2025-11-18arm: [MVE intrinsics] rework vgetq_lane vsetq_laneChristophe Lyon
2025-11-18arm: [MVE intrinsics] Avoid warnings when floating-point is not supported [PR...Christophe Lyon
2025-11-18[RISC-V] Add cpu and tuning structures for spacemit-x60 designAustin Law
2025-11-17Also handle vptestnm + and15/and3 to just vptestnm.liuhongt
2025-11-17diagnostics: fix socket includes for MinGW host [PR122666]Evgeny Karpov
2025-11-17[x86] avoid using masked vector epilogues when no scalar epilog is neededRichard Biener
2025-11-16Remove /usr/ccs references on SolarisRainer Orth
2025-11-15[RISC-V] Avoid most calls to gen_extend_insnJeff Law
2025-11-14aarch64: Remove unused patternKarl Meakin
2025-11-14aarch64: Add `aarch64_comparison_operator_cc`Karl Meakin
2025-11-14aarch64: Remove redundant checksKarl Meakin
2025-11-14aarch64: Merge mov<ALLI>cc with mov<GPF>ccKarl Meakin
2025-11-14aarch64: Fix condition accepted by mov<GPF>ccKarl Meakin
2025-11-14RISC-V: Add missing member for andes_25_tune_infoKuan-Lin Chen
2025-11-14arm: [MVE intrinsics] rework sqrshr sqshl srshr uqrshl uqshl urshrChristophe Lyon
2025-11-14arm: [MVE intrinsics] rework sqshll srshrl uqshll urshrlChristophe Lyon
2025-11-14arm: [MVE intrinsics] rework sqrshrl sqrshrl_sat48Christophe Lyon
2025-11-14arm: [MVE intrinsics] rework uqrshll uqrshll_sat48Christophe Lyon
2025-11-14arm: [MVE intrinsics] rework vpnotChristophe Lyon
2025-11-14i386: Remove 'i' from output operand constraintUros Bizjak
2025-11-14build: Require binutils 2.30+ on Solaris [PR121457, PR121458]Rainer Orth
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