From 96049fcf4e5f2eb0271bdfa89e113eef9c5fa9f6 Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Thu, 7 Mar 2024 09:50:29 -0500 Subject: [GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378) Recommits llvm/llvm-project#80378 which was reverted in llvm/llvm-project#84330. The problem was that the change in llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir used 217 as an opcode instead of a regex. --- llvm/lib/CodeGen/MachineVerifier.cpp | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp') diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 1d0757c5d7f5..ecb3bd33bdfd 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1640,6 +1640,24 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { break; } + + case TargetOpcode::G_SPLAT_VECTOR: { + LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); + LLT SrcTy = MRI->getType(MI->getOperand(1).getReg()); + + if (!DstTy.isScalableVector()) + report("Destination type must be a scalable vector", MI); + + if (!SrcTy.isScalar()) + report("Source type must be a scalar", MI); + + if (DstTy.getScalarType() != SrcTy) + report("Element type of the destination must be the same type as the " + "source type", + MI); + + break; + } case TargetOpcode::G_DYN_STACKALLOC: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &AllocOp = MI->getOperand(1); -- cgit v1.2.3