From be699bf38995f940225aa31b520be00721e258b2 Mon Sep 17 00:00:00 2001
From: Thomas Raoux <thomas.raoux@gmail.com>
Date: Tue, 20 Aug 2019 15:54:59 +0000
Subject:     [CodeGen] Add a pass to do block predication on SSA machine IR.

    For targets requiring aggressive scheduling and/or software pipeline we need to
    apply predication before preRA scheduling. This adds a pass re-using the early
    if-cvt infrastructure but generating predicated instructions instead of
    speculatively executing instructions. It allows doing if conversion on blocks
    containing instructions with side-effects. The pass re-use the target hook from
    postRA if-conversion to let the target decide on the heuristic to apply.

    Differential Revision: https://reviews.llvm.org/D66190

llvm-svn: 369395
---
 llvm/lib/CodeGen/CodeGen.cpp | 1 +
 1 file changed, 1 insertion(+)

(limited to 'llvm/lib/CodeGen/CodeGen.cpp')

diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index c37ed57781d4..c6376290dab8 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -28,6 +28,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeDetectDeadLanesPass(Registry);
   initializeDwarfEHPreparePass(Registry);
   initializeEarlyIfConverterPass(Registry);
+  initializeEarlyIfPredicatorPass(Registry);
   initializeEarlyMachineLICMPass(Registry);
   initializeEarlyTailDuplicatePass(Registry);
   initializeExpandMemCmpPassPass(Registry);
-- 
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