From ba420d8122239592a1fb7ad6efd2c186aecfdef5 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Mon, 28 Apr 2025 15:31:44 +0100 Subject: [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#136759) This patch adds support for LLVM IR atomicrmw `fmaximum` and `fminimum` instructions. These mirror the `llvm.maximum.*` and `llvm.minimum.*` instructions, but are atomic and use IEEE754 2019 handling for NaNs, which is different to `fmax` and `fmin`. See: https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic for more details. Future changes will allow this LLVM IR to be lowered to specialised assembler instructions on suitable targets, such as AArch64. --- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp') diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 73bed85c65b3..0893cf7aec8c 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -678,6 +678,10 @@ static unsigned getEncodedRMWOperation(AtomicRMWInst::BinOp Op) { case AtomicRMWInst::FSub: return bitc::RMW_FSUB; case AtomicRMWInst::FMax: return bitc::RMW_FMAX; case AtomicRMWInst::FMin: return bitc::RMW_FMIN; + case AtomicRMWInst::FMaximum: + return bitc::RMW_FMAXIMUM; + case AtomicRMWInst::FMinimum: + return bitc::RMW_FMINIMUM; case AtomicRMWInst::UIncWrap: return bitc::RMW_UINC_WRAP; case AtomicRMWInst::UDecWrap: -- cgit v1.2.3