From a88c722e687e6780dcd6a58718350dc76fcc4cc9 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 25 Sep 2020 11:45:22 +0100 Subject: [AArch64] PAC/BTI code generation for LLVM generated functions PAC/BTI-related codegen in the AArch64 backend is controlled by a set of LLVM IR function attributes, added to the function by Clang, based on command-line options and GCC-style function attributes. However, functions, generated in the LLVM middle end (for example, asan.module.ctor or __llvm_gcov_write_out) do not get any attributes and the backend incorrectly does not do any PAC/BTI code generation. This patch record the default state of PAC/BTI codegen in a set of LLVM IR module-level attributes, based on command-line options: * "sign-return-address", with non-zero value means generate code to sign return addresses (PAC-RET), zero value means disable PAC-RET. * "sign-return-address-all", with non-zero value means enable PAC-RET for all functions, zero value means enable PAC-RET only for functions, which spill LR. * "sign-return-address-with-bkey", with non-zero value means use B-key for signing, zero value mean use A-key. This set of attributes are always added for AArch64 targets (as opposed, for example, to interpreting a missing attribute as having a value 0) in order to be able to check for conflicts when combining module attributed during LTO. Module-level attributes are overridden by function level attributes. All the decision making about whether to not to generate PAC and/or BTI code is factored out into AArch64FunctionInfo, there shouldn't be any places left, other than AArch64FunctionInfo, which directly examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which is/will-be handled by a separate patch. Differential Revision: https://reviews.llvm.org/D85649 --- clang/lib/CodeGen/CodeGenModule.cpp | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'clang/lib/CodeGen/CodeGenModule.cpp') diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 6a77f6b040a1..c3457865c0b0 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -590,6 +590,23 @@ void CodeGenModule::Release() { 1); } + if (Arch == llvm::Triple::aarch64 || Arch == llvm::Triple::aarch64_32 || + Arch == llvm::Triple::aarch64_be) { + getModule().addModuleFlag(llvm::Module::Error, + "branch-target-enforcement", + LangOpts.BranchTargetEnforcement); + + getModule().addModuleFlag(llvm::Module::Error, "sign-return-address", + LangOpts.hasSignReturnAddress()); + + getModule().addModuleFlag(llvm::Module::Error, "sign-return-address-all", + LangOpts.isSignReturnAddressScopeAll()); + + getModule().addModuleFlag(llvm::Module::Error, + "sign-return-address-with-bkey", + !LangOpts.isSignReturnAddressWithAKey()); + } + if (LangOpts.CUDAIsDevice && getTriple().isNVPTX()) { // Indicate whether __nvvm_reflect should be configured to flush denormal // floating point values to 0. (This corresponds to its "__CUDA_FTZ" -- cgit v1.2.3