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2025-03-11[RISCV] Enable prefetching writes (#130561)Pengcheng Wang
We should prefetch writes since `Zicbop` has `prefetch.w`.
2025-01-29[IR] Convert from nocapture to captures(none) (#123181)Nikita Popov
This PR removes the old `nocapture` attribute, replacing it with the new `captures` attribute introduced in #116990. This change is intended to be essentially NFC, replacing existing uses of `nocapture` with `captures(none)` without adding any new analysis capabilities. Making use of non-`none` values is left for a followup. Some notes: * `nocapture` will be upgraded to `captures(none)` by the bitcode reader. * `nocapture` will also be upgraded by the textual IR reader. This is to make it easier to use old IR files and somewhat reduce the test churn in this PR. * Helper APIs like `doesNotCapture()` will check for `captures(none)`. * MLIR import will convert `captures(none)` into an `llvm.nocapture` attribute. The representation in the LLVM IR dialect should be updated separately.
2025-01-20[LoongArch] Impl TTI hooks for LoongArch to support LoopDataPrefetch pass ↵ZhaoQi
(#118437) Inspired by https://reviews.llvm.org/D146600, this commit adds some TTI hooks for LoongArch to make LoopDataPrefetch pass really work. Including: - `getCacheLineSize()`: 64 for loongarch64. - `getPrefetchDistance()`: After testing SPEC CPU 2017, improvements taken by prefetching are more obvious when set PrefetchDistance to 200(results shown blow), although different benchmarks fit for different best choice. - `enableWritePrefetching()`: store prefetch is supported by LoongArch, so set WritePrefetching to true in default. - `getMinPrefetchStride()` and `getMaxPrefetchIterationsAhead()` still use default values: 1 and UINT_MAX, so not override them. After this commit, the test added by https://reviews.llvm.org/D146600 can generate llvm.prefetch intrinsic IR correctly. Results of spec2017rate benchmarks (testing date: ref, copies: 1): - For all C/C++ benchmarks, compared to O3+novec/lsx/lasx, prefetch can bring about -1.58%/0.31%/0.07% performance improvement for int benchmarks and 3.26%/3.73%/3.78% improvement for floating point benchmarks. (Only O3+novec+prefetch decreases when testing intrate.) - But prefetch results in performance reduction almost for every Fortran benchmark compiled by flang. While considering all C/C++/Fortran benchmarks, prefetch performance will decrease about 1% ~ 5%. FIXME: Keep `loongarch-enable-loop-data-prefetch` option default to false for now due to the bad effect for Fortran.
2024-05-14[test][LoongArch] Add -mattr=+d option. NFCwanglei
Because most of tests assume target-abi=`lp64d`, adding the corresponding feature is reasonable. rg -l loongarch -g '!*.s' | xargs sed -i '/mtriple=loongarch/ {/-mattr=/!{/target-abi/! s/mtriple=loongarch.. /&-mattr=+d /}}'
2023-11-10[RISCV] Enable LoopDataPrefetch pass (#66201)Wang Pengcheng
So that we can benefit from data prefetch when `Zicbop` extension is supported. Tune information for data prefetching are added in `RISCVTuneInfo`.
2023-10-24BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreadsMatthias Braun
BlockFrequencyInfo calculates block frequencies as Scaled64 numbers but as a last step converts them to unsigned 64bit integers (`BlockFrequency`). This improves the factors picked for this conversion so that: * Avoid big numbers close to UINT64_MAX to avoid users overflowing/saturating when adding multiply frequencies together or when multiplying with integers. This leaves the topmost 10 bits unused to allow for some room. * Spread the difference between hottest/coldest block as much as possible to increase precision. * If the hot/cold spread cannot be represented loose precision at the lower end, but keep the frequencies at the upper end for hot blocks differentiable.
2023-09-18[SCEV] Fix incorrect nsw inference for multiply of addrec (#66500)Nikita Popov
SCEV currently preserves the nsw flag when performing an nsw multiply of an nsw addrec. While this is legal for nuw, this is not generally the case for nsw. This is because nsw mul does not distribute over nsw add: https://alive2.llvm.org/ce/z/mergCt Instead, we need either both nuw and nsw to be set (https://alive2.llvm.org/ce/z/7wpgGc) or explicitly prove that the distributed multiplications are also nsw (https://alive2.llvm.org/ce/z/wef9su). Fixes https://github.com/llvm/llvm-project/issues/66066.
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta
This is a follow-up to b71edfaa4ec3c998aadb35255ce2f60bba2940b0 since I forgot the lit.local.cfg files in that one. Reformatting is done with `black`. If you end up having problems merging this commit because you have made changes to a python file, the best way to handle that is to run git checkout --ours <yourfile> and then reformat it with black. If you run into any problems, post to discourse about it and we will try to help. RFC Thread below: https://discourse.llvm.org/t/rfc-document-and-standardize-python-code-style Reviewed By: barannikov88, kwk Differential Revision: https://reviews.llvm.org/D150762
2023-03-24[LoongArch] Enable LoopDataPrefetch passXiaodong Liu
Keep `EnableLoopDataPrefetch` option off for now because we need a few more TTIs and ISels. This patch is inspired by http://reviews.llvm.org/D17943. Reviewed By: SixWeining Differential Revision: https://reviews.llvm.org/D146600
2023-01-05[Transforms] Convert some tests to opaque pointers (NFC)Nikita Popov
These are all tests where conversion worked automatically, and required no manual fixup.
2022-12-08[NFC] Port all LoopDataPrefetch tests to `-passes=` syntaxRoman Lebedev
2022-12-01[test] Switch to use -passes syntax in various test casesBjorn Pettersson
2022-07-26[LoopDataPrefetch] Fix crash when TTI doesn't set CacheLineSizezhongyunde
Fix https://github.com/llvm/llvm-project/issues/56681 Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D130418
2021-08-26[LoopDataPrefetch] Add missed LoopSimplify dependence for prefetch passAndrew Wei
SCEVExpander::expandCodeFor may expand add recurrences for loop with a preheader, so we should make LoopDataPrefetch dependent on LoopSimplify. This patch will try to fix : https://bugs.llvm.org/show_bug.cgi?id=43784 Reviewed By: Meinersbur Differential Revision: https://reviews.llvm.org/D108448
2020-07-28Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"Jinsong Ji
This reverts commit bf544fa1c3cb80f24d85e84559fb11193846259f. Fixed the typo in PPCInstrInfo.cpp.
2020-07-27Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"Jinsong Ji
This reverts commit adffce71538e219aab4eeb024819baa7687262ff. This is breaking test-suite, revert while investigation.
2020-07-27[PowerPC] Remove QPX/A2Q BGQ/BGP CNK supportJinsong Ji
Per RFC http://lists.llvm.org/pipermail/llvm-dev/2020-April/141295.html no one is making use of QPX/A2Q/BGQ/BGP CNK anymore. This patch remove the support of QPX/A2Q in llvm, BGQ/BGP in clang, CNK support in openmp/polly. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D83915
2019-04-17Revert "Temporarily Revert "Add basic loop fusion pass.""Eric Christopher
The reversion apparently deleted the test/Transforms directory. Will be re-reverting again. llvm-svn: 358552
2019-04-17Temporarily Revert "Add basic loop fusion pass."Eric Christopher
As it's causing some bot failures (and per request from kbarton). This reverts commit r358543/ab70da07286e618016e78247e4a24fcb84077fda. llvm-svn: 358546
2018-05-09[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen
In order to set breakpoints on labels and list source code around labels, we need collect debug information for labels, i.e., label name, the function label belong, line number in the file, and the address label located. In order to keep these information in LLVM IR and to allow backend to generate debug information correctly. We create a new kind of metadata for labels, DILabel. The format of DILabel is !DILabel(scope: !1, name: "foo", file: !2, line: 3) We hope to keep debug information as much as possible even the code is optimized. So, we create a new kind of intrinsic for label metadata to avoid the metadata is eliminated with basic block. The intrinsic will keep existing if we keep it from optimized out. The format of the intrinsic is llvm.dbg.label(metadata !1) It has only one argument, that is the DILabel metadata. The intrinsic will follow the label immediately. Backend could get the label metadata through the intrinsic's parameter. We also create DIBuilder API for labels to be used by Frontend. Frontend could use createLabel() to allocate DILabel objects, and use insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR. Differential Revision: https://reviews.llvm.org/D45024 Patch by Hsiangkai Wang. llvm-svn: 331841
2016-08-22[PM] Port LoopDataPrefetch AArch64 tests to new pass managerBalaram Makam
Reviewers: mcrosier, tejohnson Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D23724 llvm-svn: 279431
2016-08-13[PM] Port LoopDataPrefetch to new pass managerTeresa Johnson
Summary: Refactor the existing support into a LoopDataPrefetch implementation class and a LoopDataPrefetchLegacyPass class that invokes it. Add a new LoopDataPrefetchPass for the new pass manager that utilizes the LoopDataPrefetch implementation class. Reviewers: mehdi_amini Subscribers: sanjoy, mzolotukhin, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23483 llvm-svn: 278591
2016-07-22[LoopDataPrefetch] Include hotness of region in opt remarkAdam Nemet
llvm-svn: 276488
2016-06-21[Kryo] Enable loop prefetcher.Haicheng Wu
Differential Revision: http://reviews.llvm.org/D21535 llvm-svn: 273329
2016-05-05[LoopDataPrefetch] Add optimization remarkAdam Nemet
With -Rpass=loop-data-prefetch, show the memory access that got prefetched. llvm-svn: 268578
2016-03-29[LoopDataPrefetch] Centralize the tuning cl::opts under the passAdam Nemet
This is effectively NFC, minus the renaming of the options (-cyclone-prefetch-distance -> -prefetch-distance). The change was requested by Tim in D17943. llvm-svn: 264806
2016-03-18[LoopDataPrefetch] Add TTI to limit the number of iterations to prefetch aheadAdam Nemet
Summary: It can hurt performance to prefetch ahead too much. Be conservative for now and don't prefetch ahead more than 3 iterations on Cyclone. Reviewers: hfinkel Subscribers: llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D17949 llvm-svn: 263772
2016-03-18[LoopDataPrefetch/Aarch64] Allow selective prefetching of large-strided accessesAdam Nemet
Summary: And use this TTI for Cyclone. As it was explained in the original RFC (http://thread.gmane.org/gmane.comp.compilers.llvm.devel/92758), the HW prefetcher work up to 2KB strides. I am also adding tests for this and the previous change (D17943): * Cyclone prefetching accesses with a large stride * Cyclone not prefetching accesses with a small stride * Generic Aarch64 subtarget not prefetching either Reviewers: hfinkel Subscribers: aemerson, rengolin, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D17945 llvm-svn: 263771
2016-02-22[LoopDataPrefetch] Make it testable with optAdam Nemet
Summary: Since this is an IR pass it's nice to be able to write tests without llc. This is the counterpart of the llc test under CodeGen/PowerPC/loop-data-prefetch.ll. Reviewers: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17464 llvm-svn: 261578