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AgeCommit message (Expand)Author
2025-07-03Revert "[mlgo][regalloc] Fix after PR #131837" (#146897)Mircea Trofin
2025-07-03[X86] fp128-select.ll - remove CFI noiseSimon Pilgrim
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David
2025-07-03[WebAssembly] Fold TargetGlobalAddress with added offset (#145829)jjasmine
2025-07-03Revert "[win][aarch64] Always reserve frame pointers for Arm64 Windows" (#146...David Spickett
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa
2025-07-03[ARM] Add neon vector support for truncDavid Green
2025-07-03[RISCV] Add isel patterns for generating XAndesPerf branch immediate instruct...Jim Lin
2025-07-02[RISCV] Add additional gather/scatter addressing coveragePhilip Reames
2025-07-02[SDAG] Prefer scalar for prefix of vector GEP expansion (#146719)Philip Reames
2025-07-03[RISCV][VLOPT] Support v[f]slide1up.v{x,f} (#146716)Luke Lau
2025-07-02[RISCV][VLOPT] Support vslide{up,down} (#146710)Luke Lau
2025-07-02[RISCV][VLOPT] Add support for vfmerge.vfm and vfmv.v.f (#146692)Luke Lau
2025-07-03WebAssembly: Move validation of EH flags to TargetMachine construct time (#14...Matt Arsenault
2025-07-02[win][aarch64] Always reserve frame pointers for Arm64 Windows (#146582)Daniel Paoliello
2025-07-02[PowerPC] Fix ppc-reduce-cr-ops mishandling of subregister uses (#144405)Lei Huang
2025-07-02[SPIRV] Add option to add all KHR extensions (#145535)Steven Perron
2025-07-02[X86] Add BLEND/UNPCK shuffles to canCreateUndefOrPoisonForTargetNode/isGuara...Simon Pilgrim
2025-07-02[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637)Craig Topper
2025-07-02[HLSL][SPRIV] Handle signed RWBuffer correctly (#144774)Steven Perron
2025-07-02[Xtensa] Implement THREADPTR and DFPAccel Xtensa Options. (#145543)Andrei Safronov
2025-07-02[SystemZ][HLASM] Emit END instruction (#146110)Kai Nacke
2025-07-02[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG C...woruyu
2025-07-02[SPIRV] Add FloatControl2 capability (#144371)Steven Perron
2025-07-02[GlobalISel] Allow expansion of urem by constant in prelegalizer (#145914)jyli0116
2025-07-02[AMDGPU] Add a debug option `-amdgpu-snop-padding` for `GCNHazardRecognizer` ...Shilei Tian
2025-07-02[LV] Add support for partial reductions without a binary op (#133922)David Sherwood
2025-07-02[Xtensa] Implement lowering SELECT_CC/BRCC for Xtensa FP Option. (#145544)Andrei Safronov
2025-07-02[LLVM][AArch64] Relax SVE/SME codegen predicates. (#145322)Paul Walker
2025-07-02[DAG] visitFREEZE - always allow freezing multiple operands (#145939)Simon Pilgrim
2025-07-02[LoongArch] Pre-commit for optimizing insert extracted pair elementsQi Zhao
2025-07-01[WebAssembly] Fix inline assembly with vector types (#146574)Alex Crichton
2025-07-01[WebAssembly] Fold any/alltrue (setcc x, 0, eq/ne) to [not] any/alltrue x (#1...jjasmine
2025-07-01[WebAssembly] [Backend] Wasm optimize illegal bitmask (#145627)jjasmine
2025-07-01[SelectionDAG] Fix NaN regression in fma dag-combine. (#146592)James Y Knight
2025-07-01[NVPTX] Further cleanup call isel (#146411)Alex MacLean
2025-07-01AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive...Changpeng Fang
2025-07-01[X86] freeze-vector.ll - fix cut+pasta typo in frozen build vector testsSimon Pilgrim
2025-07-01[AMDGPU][SIInsertWaitCnts] skip meta instructions early (#145720)Sameer Sahasrabuddhe
2025-07-01[PHIElimination] Verify reappropriated COPY is of similar register class, upd...Guy David
2025-07-01[AMDGPU] Fix wrong reverse operations for `v_cmpx_le_u32` (#146398)Shilei Tian
2025-07-01[X86] legalize-sub-zero.ll - regenerate test checksSimon Pilgrim
2025-07-01[AArch64] Fix ldp rename through a bundle (#146415)David Green
2025-07-01[ARM] Add neon vector support for ceilDavid Green
2025-07-01[NFC][AMDGPU] Pre-commit a test case that shows wrong reverse operation is us...Shilei Tian
2025-07-01[NFC][AMDGPU] Auto generate check lines for some test cases (#146400)Shilei Tian
2025-07-01[Hexagon] Implement shouldConvertConstantLoadToIntImm (#146452)Sudharsan Veeravalli
2025-07-01[DAG] canCreateUndefOrPoison - add handling for CTTZ/CTLZ_ZERO_UNDEF nodes (#...Simon Pilgrim
2025-07-01[RISCV] Fix typo in header of llvm/test/CodeGen/RISCV/rvv/select-fp.ll. NFC.Jim Lin
2025-07-01[X86] freeze-unary.ll - remove unnecessary freeze from CTLZ/CTTZ_ZERO_UNDEF t...Simon Pilgrim
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