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2025-09-10Revert "[DAGCombiner] Relax condition for extract_vector_elt combine" (#157953)Arthur Eubanks
2025-09-10[AMDGPU] NFC. Add testcase to test SIInsertWaitcnts::generateWaitcntInstBefor...choikwa
2025-09-10[RISCV][GISel] Widen G_ABDS/G_ABDU before lowering when Zbb is enabled. (#157...Craig Topper
2025-09-10[DirectX] Removing dxbc DescriptorRange from mcbxdc (#154629)joaosaffran
2025-09-10[RISCV] Extend zvqdot matching to handle disjoint or (#157901)Hongyu Chen
2025-09-10[RISCV] Fold (X & -(1 << C1) & 0xffffffff) == C2 << C1 to sraiw X, C1 == C2. ...Craig Topper
2025-09-10[AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395)Aaditya
2025-09-10[GISel] Combine shift + trunc + shift pattern (#155583)jyli0116
2025-09-10[AMDGPU] Extending wave reduction intrinsics for `i64` types - 3 (#151310)Aaditya
2025-09-10[AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (#157810)Fabian Ritter
2025-09-10[AMDGPU] Extending wave reduction intrinsics for `i64` types - 2 (#151309)Aaditya
2025-09-10[x86][AVX-VNNI] Fix VPDPBUSD Argument Types (#155194)BaiXilin
2025-09-10[CodeGen] Fix handling dead redefs in finalizeBundle (#157427)Jay Foad
2025-09-10[AMDGPU] Extending wave reduction intrinsics for `i64` types - 1 (#150169)Aaditya
2025-09-10[AMDGPU][gfx1250] Support "cluster" syncscope (#157641)Pierre van Houtryve
2025-09-10[AMDGPU] Treat GEP offsets as signed in AMDGPUPromoteAlloca (#157682)Fabian Ritter
2025-09-10[AMDGPU][gfx1250] Remove SCOPE_SE for scratch stores (#157640)Pierre van Houtryve
2025-09-10[PowerPC] Extend and update the test for `half` support (NFC) (#152625)Trevor Gross
2025-09-10[AMDGPU] Change expand-fp opt level argument syntax (#157408)Frederik Harwath
2025-09-10[X86][Test] Update tests for `lround` and `llrint` (NFC) (#157807)Trevor Gross
2025-09-10[X86] Recognise VPMADD52L pattern with AVX512IFMA/AVXIFMA (#153787) (#156714)Justin Riddell
2025-09-10Revert "[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)" (#157639)Pierre van Houtryve
2025-09-10[AMDGPU][gfx1250] Implement SIMemoryLegalizer (#154726)Pierre van Houtryve
2025-09-10[DAGCombiner] Relax condition for extract_vector_elt combine (#157658)ZhaoQi
2025-09-10[WebAssembly] extadd_pairwise for PartialReduce (#157669)Sam Parker
2025-09-10[X86][LiveRegUnits] Exclude reserved registers from TargetRegisterClass (#157...Phoebe Wang
2025-09-09[RISCV] Add VendorXTHeadCondMov to useInversedSetcc. (#157758)Craig Topper
2025-09-10[AArch64] Lower zero cycle FPR zeroing (#156261)Tomer Shafir
2025-09-09[RISCV] Add coverage for select with minmax arm [nfc] (#157539)Philip Reames
2025-09-09[PowerPC] Support `-fpatchable-function-entry` on PPC64LE (#151569)Maryam Moghadas
2025-09-09[clang][driver][arm][macho] Default to -mframe-pointer=non-leaf. (#154216)Francesco Petrogalli
2025-09-09[MachineOutliner] Add profile guided outlining (#154437)Ellis Hoag
2025-09-09[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#1...Craig Topper
2025-09-09[RISCV] Add TH_EXT(U) to hasAllNBitUsers in RISCVOptWInstrs. (#157544)Craig Topper
2025-09-09[HLSL][DirectX] Add support for `rootsig` as a target environment (#156373)Finn Plummer
2025-09-09[AMDGPU][True16][CodeGen] Fixed two lit tests (#157684)Brox Chen
2025-09-09[RISCV] Exclude LPAD in machine outliner (#157220)Jesse Huang
2025-09-09[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#...Brox Chen
2025-09-09[AArch64][GlobalISel] Add test coverage for arm64-vcvtxd_f32_f64.ll. NFCDavid Green
2025-09-09AArch64: Fix codegen test in MC directory (#157648)Matt Arsenault
2025-09-09[AArch64][SME] Support agnostic ZA functions in the MachineSMEABIPass (#149064)Benjamin Maxwell
2025-09-09[RISCV] Replace undef with poison, NFC (#157396)Jianjian Guan
2025-09-09[AArch64] Use unsigned variant of `<s|u>addv_64` SVE vector reduction intrins...Rajveer Singh Bharadwaj
2025-09-09[RISCV] Loosen the requirement of shadow stack codegen to Zimop (#152251)Jesse Huang
2025-09-09X86: Use LiveRegUnits in findDeadCallerSavedReg (#156817)Matt Arsenault
2025-09-09[RISCV] Undo fneg (fmul x, y) -> fmul x, (fneg y) transform (#157388)Luke Lau
2025-09-08[AMDGPU] Add MSG_RTN_GET_CLUSTER_BARRIER_STATE (#157549)Stanislav Mekhanoshin
2025-09-08[AMDGPU] Update hard-clauses-load-monitor.mir. NFC (#157546)Stanislav Mekhanoshin
2025-09-08[AMDGPU] High VGPR emission tests. NFC. (#157534)Stanislav Mekhanoshin
2025-09-08[AMDGPU] Constrain inline asm vgprs to low 256 (#157531)Stanislav Mekhanoshin
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