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2025-10-07simplify test. The next step is to add debug logusers/mingmingl-llvm/annotator-backupusers/mingmingl-llvm/annotatormingmingl
2025-10-05simplify testusers/mingmingl/llvm/annotator-backupmingmingl
2025-10-05run 'git merge main'mingmingl
2025-10-06[clang][NVPTX] Add intrinsics and builtins for CVT RS rounding mode (#160494)Srinivasa Ravi
2025-10-05[NFC] Remove accidently added file in #161758 (#161991)Pranav Kant
2025-10-05[InstSimplify] Simplify fcmp implied by dominating fcmp (#161090)Yingwei Zheng
2025-10-04[RegAlloc] Remove default restriction on non-trivial rematerialization (#159211)Luke Lau
2025-10-04[MC] Make .note.GNU-stack explicit for the trampoline case (#151754)ssijaric-nv
2025-10-04[ARM] Update and cleanup lround/llround tests. NFCDavid Green
2025-10-04[AMDGPU] Add another test for missing S_WAIT_XCNT (#161838)Jay Foad
2025-10-04AMDGPU: Remove LDS_DIRECT_CLASS register class (#161762)Matt Arsenault
2025-10-04AMDGPU: Remove m0 classes (#161758)Matt Arsenault
2025-10-03[AMDGPU][True16][CodeGen] fix v_mov_b16_t16 index in folding pass (#161764)Brox Chen
2025-10-03[SPIR-V] Fix `asdouble` issue in SPIRV codegen to correctly generate `OpBitCa...Lucie Choi
2025-10-03[LLVM][CodeGen] Check Non Saturate Case in isSaturatingMinMax (#160637)Yatao Wang
2025-10-03[AArch64][GlobalISel] Use TargetConstant for shift immediates (#161527)David Green
2025-10-03[Hexagon] Support lowering of setuo & seto for vector types in Hexagon (#158740)Fateme Hosseini
2025-10-03[Hexagon] isel-fold-shl-zext.ll - regenerate test checks (#161869)Simon Pilgrim
2025-10-03[AMDGPU][Attributor] Stop inferring amdgpu-no-flat-scratch-init in sanitized ...Chaitanya
2025-10-03[x86] lowerV4I32Shuffle - don't adjust PSHUFD splat masks to match UNPCK (#16...Simon Pilgrim
2025-10-04AMDGPU: Fix broken register class IDs in mir tests (#161832)Matt Arsenault
2025-10-03[RISCV] Support scalar llvm.fmodf intrinsic. (#161743)Craig Topper
2025-10-03[AMDGPU] Enable XNACK on gfx1250 (#161457)Shilei Tian
2025-10-03Fold SVE mul and mul_u to neg during isel (#160828)Martin Wehking
2025-10-03[Hexagon] Added lowering for sint_to_fp from v32i1 to v32f32 (#159507)pkarveti
2025-10-03[X86] Fold ADD(x,x) -> X86ISD::VSHLI(x,1) (#161843)Simon Pilgrim
2025-10-03[SPARC] Prevent meta instructions from being inserted into delay slots (#161111)Koakuma
2025-10-03AMDGPU: Fix constrain register logic for physregs (#161794)Matt Arsenault
2025-10-03[AArch64][SME] Enable `aarch64-split-sve-objects` with hazard padding (#161714)Benjamin Maxwell
2025-10-03[X86][GlobalIsel] Adds support for G_UMIN/G_UMAX/G_SMIN/G_SMAX (#161783)Mahesh-Attarde
2025-10-03[X86][GlobalIsel] Enable gisel run for fpclass isel (#160741)Mahesh-Attarde
2025-10-03[AMDGPU] Account for implicit XCNT insertion (#160812)Aaditya
2025-10-03[AMDGPU] Define VS_128*. NFCI (#161798)Stanislav Mekhanoshin
2025-10-03[ARM] shouldFoldMaskToVariableShiftPair should be true for scalars up to the ...AZero13
2025-10-03[X86] combineBitcastvxi1 - bail out on soft-float targets (#161704)Simon Pilgrim
2025-10-03[X86][AMX] Combine constant zero vector and AMX cast to tilezero (#92384)Phoebe Wang
2025-10-02[ARM] Update and cleanup lrint/llrint tests. NFCDavid Green
2025-10-02[AMDGPU] Be less optimistic when allocating module scope lds (#161464)Jon Chesterfield
2025-10-02[NVPTX] expand trunc/ext on v2i32 (#161715)Artem Belevich
2025-10-02[AArch64][SME] Support split ZPR and PPR area allocation (#142392)Benjamin Maxwell
2025-10-02[RegAlloc] Add coverage leading to revert of pr160765 (#161614)Philip Reames
2025-10-02[AMDGPU] s_quadmask* implicitly defines SCC (#161582)LU-JOHN
2025-10-02[X86] Create special case for (a-b) - (a<b) -> sbb a, b (#161388)AZero13
2025-10-02[Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618)Ikhlas Ajbar
2025-10-02Greedy: Take hints from copy to physical subreg (#160467)Matt Arsenault
2025-10-02[Codegen] Add a separate stack ID for scalable predicates (#142390)Benjamin Maxwell
2025-10-02AMDGPU: Switch test to generated checks (#161658)Matt Arsenault
2025-10-02RegAllocGreedy: Check if copied lanes are live in trySplitAroundHintReg (#160...Matt Arsenault
2025-10-02[LLVM][CodeGen][SVE] Remove failure cases when widening vector load/store ops...Paul Walker
2025-10-02[SPIR-V] Prevent adding duplicate binding instructions for implicit binding (...Lucie Choi
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