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path: root/llvm/test/CodeGen/VE/Vector
AgeCommit message (Expand)Author
2025-04-22Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value ...zhijian lin
2024-12-15[VE,test] Change llc -march= to -mtriple=Fangrui Song
2023-08-18[VE] Change the way of lowering storeKazushi (Jam) Marukawa
2023-08-17[VE] Avoid vectorizing store/load in scalar modeKazushi (Jam) Marukawa
2023-05-12[DAGCombiner][AArch64][VE] Teach BuildUDIV/SDIV to use 2x mul when mulh/mul_l...Craig Topper
2022-12-19[VE] Convert some tests to opaque pointers (NFC)Nikita Popov
2022-11-15[SDAG] avoid udiv/urem transform for vector/scalar type mismatchesSanjay Patel
2022-10-15[CodeGen] Using ZExt for extractelement indices.Peter Rong
2022-09-16[VP][VE] Default VP_SREM/UREM to Expand and add generic expansion using VP_SD...Craig Topper
2022-07-19[VE] Support load/store/spill of vector mask registersKazushi (Jam) Marukawa
2022-07-01[VE] Support load/store vm regsitersKazushi (Jam) Marukawa
2022-04-06Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"Daniil Kovalev
2022-04-06[CodeGen] Place SDNode debug ID declaration under appropriate #ifDaniil Kovalev
2022-03-22[VP] Preserve address space of pointer for strided load/store intrinsics.Craig Topper
2022-03-16[VE] Remove output to /dev/stdoutJake Egan
2022-03-16[VE] v512|256 f32|64 fneg isel and testsSimon Moll
2022-03-15[VE] strided v256.23 isel and testsSimon Moll
2022-03-14[VE] v256f32|64 fma iselSimon Moll
2022-03-14[VE] v256i32|64 reduction isel and testsSimon Moll
2022-03-14[VE] v256.32|64 gather|scatter isel and testsSimon Moll
2022-03-02[VE] (masked) load|store v256.32|64 iselSimon Moll
2022-02-18[VE] Enable v256 fcmp true|false testsSimon Moll
2022-02-15[VE] v256i1 broadcast isel and testsSimon Moll
2022-02-14[VE] v256i1 and|or|xor isel and testsSimon Moll
2022-02-08[VE] v256.32|64 setcc isel and testsSimon Moll
2022-01-18[VE] vp_select+vectorBinOp passthru isel and testsSimon Moll
2022-01-17[VE] select|vp.merge|vp.select v256 isel and testsSimon Moll
2021-12-21[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and testsSimon Moll
2021-12-21[VE] U|SDIV v256i32|64 isel and testsSimon Moll
2021-12-15[VE] SHL,SRA,SRL v256i32|64 isel and testsSimon Moll
2021-12-14[VE] MUL,SUB,OR,XOR v256i32|64 iselSimon Moll
2021-12-01[VE][NFC] Use POSIX-compatible stream redirectionSimon Moll
2021-01-08[VP] ISD helper functions [VE] isel for vp_add, vp_andSimon Moll
2021-01-08[VE] Expand single-element BUILD_VECTOR to INSERT_VECTOR_ELTSimon Moll
2021-01-08[VE] Extract & insert vector element iselSimon Moll
2020-12-23[VE] Vector 'and' isel and testsSimon Moll
2020-12-21[VE] Correct VMP allocation in calling convKazushi (Jam) Marukawa
2020-12-19[VE] Support copy of vector mask registersKazushi (Jam) Marukawa
2020-12-10[VE][NFC] Disable VP testsKazushi (Jam) Marukawa
2020-12-09[VP] Build VP SDNodesSimon Moll
2020-11-30[VE] Optimize prologue/epilogue instructionsKazushi (Jam) Marukawa
2020-11-30[VE] Change the behaviour of truncateKazushi (Jam) Marukawa
2020-11-23[VE] VE Vector Predicated SDNode, vector add isel and testsSimon Moll
2020-11-19[VE] VEC_BROADCAST, lowering and iselSimon Moll
2020-11-17[VE] Optimize leaf functionsKazushi (Jam) Marukawa
2020-11-16[VE] fastcc and vreg-to-vreg copySimon Moll
2020-11-04[VE] Add +vpu attributeSimon Moll