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path: root/llvm/test/CodeGen/MIR
AgeCommit message (Expand)Author
2025-06-27[NVPTX] Fixup v2i8 parameter and return lowering (#145585)Alex MacLean
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus
2025-06-23[NVPTX] Rename register classes after float register removal (NFC) (#145255)Alex MacLean
2025-06-06[MIRParser] Report register class errors in a deterministic order (#142928)Jay Foad
2025-05-29[NVPTX] Cleanup ISel code after float register removal, use BasicNVPTXInst (#...Alex MacLean
2025-05-21[NVPTX] Remove Float register classes (#140487)Alex MacLean
2025-05-13[NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (#...Drew Kersnar
2025-05-08[CodeGen] Parse nusw flag (#138856)Pierre van Houtryve
2025-05-06[AArch64] Correct position of CFI Instruction for Pointer Authentication (#13...Daniel Kiss
2025-04-15[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)Jun Wang
2025-04-04[Verifier] Require that dbg.declare variable is a ptr (#134355)Nikita Popov
2025-03-27[YAML] fix output incorrect format for block scalar string (#132897)Congcong Cai
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus
2025-03-17AMDGPU: Migrate more tests away from undef (#131314)Matt Arsenault
2025-03-15MIR: Replace undef with poison in some MIR tests (#131282)Matt Arsenault
2025-03-13[CodeGen][NPM] Port BranchFolder to NPM (#128858)Akshat Oke
2025-03-08[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)Shilei Tian
2025-03-06[win] NFC: Rename `EHCatchret` to `EHCont` to allow for EH Continuation targe...Daniel Paoliello
2025-03-03[win] Enable test/CodeGen/MIR/AArch64 on Windows (#122832)Daniel Paoliello
2025-03-03[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)Akshat Oke
2025-02-27[NVPTX] Combine addressing-mode variants of ld, st, wmma (#129102)Alex MacLean
2025-02-20[NVPTX] Remove redundant addressing mode instrs (#128044)Alex MacLean
2025-02-10MachineCopyPropagation: Do not remove copies preserved by regmask (#125868)Jinsong Ji
2025-01-28[Clang] Cleanup docs and comments relating to -fextend-variable-liveness (#12...Stephen Tozer
2025-01-23[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)Lucas Ramirez
2025-01-17[AMDGPU] Fix printing hasInitWholeWave in mir (#123232)Stanislav Mekhanoshin
2025-01-13Reapply "[aarch64][win] Add support for import call optimization (equivalent ...Daniel Paoliello
2025-01-13Revert "[aarch64][win] Add support for import call optimization (equivalent t...Kirill Stoimenov
2025-01-11[aarch64][win] Add support for import call optimization (equivalent to MSVC /...Daniel Paoliello
2025-01-06[AArch64] Correct position of CFI Instruction for Pointer Authentication (#12...Jack Styles
2024-12-18[AMDGPU] Make max dwords of memory cluster configurable (#119342)Ruiling, Song
2024-12-15[test] Change llc -march= to -mtriple=Fangrui Song
2024-12-15[test] Remove redundant -march=x86-64 when target triple is specified in IRFangrui Song
2024-12-15[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64Fangrui Song
2024-12-15[NVPTX,test] Change llc -march= to -mtriple=Fangrui Song
2024-12-15[Hexagon,test] Change llc -march= to -mtriple=Fangrui Song
2024-12-10[test] Change llc -march=mips* to -mtriple=mips*Fangrui Song
2024-11-11[RISCV][MIR] Move skip-mir-comment-trailing-whitespace.mir into RISCV subdire...Michael Maitland
2024-11-11[MIRLexer][RISCV] Eat a space after the Machine comment (#115365)Michael Maitland
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-11-07Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)dyung
2024-11-07[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (#115291)Akshat Oke
2024-11-05[AMDGPU] Fix 3495d04 MIR test (#114963)Akshat Oke
2024-11-05[AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)Akshat Oke
2024-10-30Revert "[GlobalISel] Import samesign flag" (#114256)Thorsten Schütt
2024-10-30[GlobalISel] Import samesign flag (#113090)Thorsten Schütt
2024-10-28[AArch64][Libunwind] Add Support for FEAT_PAuthLR DWARF Instruction (#112171)Jack Styles
2024-10-21Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)Akshat Oke
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