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Age	Commit message (Expand)	Author
2025-03-15	MIR: Replace undef with poison in some MIR tests (#131282)	Matt Arsenault
2024-02-05	[CodeGen] Convert tests to opaque pointers (NFC)	Nikita Popov
2023-05-17	[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm	Tobias Hieta
2021-06-30	CodeGen: Print/parse LLTs in MachineMemOperands	Matt Arsenault
2019-09-13	[PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC	Jinsong Ji
2019-09-12	[PowerPC][MCP][NFC] Pre-commit test cases for https://reviews.llvm.org/D65267	Kai Luo
2019-09-11	[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...	Guillaume Chatelet
2019-08-02	[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register	Kai Luo
2019-07-22	[PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsli	Kai Luo
2018-11-09	[Power9] Allow gpr callee saved spills in prologue to vectors registers	Zaara Syeda
2018-04-19	[if-converter] Handle BBs that terminate in ret during diamond conversion	Krzysztof Parzyszek
2018-01-31	Followup on Proposal to move MIR physical register namespace to '$' sigil.	Puyan Lotfi
2016-08-24	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	Matthias Braun
2016-07-16	llc: Add support for -run-pass none	Matthias Braun
2016-07-13	[MIR] Print on the given output instead of stderr.	Quentin Colombet
2016-02-19	When printing MIR, output to errs() rather than outs().	Justin Lebar
2015-09-10	Fix PR 24724 - The implicit register verifier shouldn't assume certain operand	Alex Lorenz