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path: root/llvm/test/CodeGen/MIR/Generic
AgeCommit message (Expand)Author
2025-03-15MIR: Replace undef with poison in some MIR tests (#131282)Matt Arsenault
2025-03-03[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)Akshat Oke
2024-10-14[MIR] Serialize virtual register flags (#110228)Akshat Oke
2024-10-04[LLVM] Add HasFakeUses to MachineFunction (#110097)Stephen Tozer
2024-09-25[MIR] Fix return value when computed properties conflict with given prop (#10...Dominik Montada
2024-09-24[MIR] Allow overriding isSSA, noPhis, noVRegs in MIR input (#108546)Dominik Montada
2024-07-15[CodeGen][NewPM] Port `MachineVerifier` to new pass manager (#98628)paperchalice
2024-07-10[MIR] Replace bespoke DIExpression parserScott Linder
2024-06-25[LLVM][MIR] Support parsing bfloat immediates in MIR parser (#96010)Stephen Chou
2024-06-07[NewPM][CodeGen] Port `regallocfast` to new pass manager (#94426)paperchalice
2024-05-01[MIR] Serialize MachineFrameInfo::isCalleeSavedInfoValid() (#90561)David Tellenbach
2024-02-05[CodeGen] Convert tests to opaque pointers (NFC)Nikita Popov
2023-11-02[CodeGen][MIR] Support parsing of scalable vectors in MIR (#70893)Michael Maitland
2023-10-17[YAMLParser] Improve plain scalar spec compliance (#68946)akirchhoff-modular
2023-08-02[DebugInfo] Fix crash when printing malformed DBG machine instructionsJay Foad
2023-07-13Revert "[CodeGen] Store SP adjustment in MachineBasicBlock. NFCI."Oliver Stannard
2023-07-12[CodeGen] Store SP adjustment in MachineBasicBlock. NFCI.Jay Foad
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta
2022-12-22[MIR] Convert tests to opaque pointers (NFC)Nikita Popov
2022-08-16Untangle the mess which is MachineBasicBlock::hasAddressTaken().Eli Friedman
2022-06-02[IR] Enable opaque pointers by defaultNikita Popov
2022-04-22MIR: Serialize FunctionContextIdx in MachineFrameInfoMatt Arsenault
2022-02-24[MIRParser] Diagnose too large align values in MachineMemOperandsJay Foad
2021-06-28[MIRParser] Add machine metadata.Michael Liao
2021-03-21MIR: Fix missing serialization for HasTailCallMatt Arsenault
2021-03-04Revert "[DebugInfo] Add new instruction and DIExpression operator for variadi...Stephen Tozer
2021-03-04[DebugInfo] Add new instruction and DIExpression operator for variadic debug ...gbtozers
2021-02-18MIR: Fix parser crash on syntax error on first characterMatt Arsenault
2020-09-03[MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo)Puyan Lotfi
2020-06-24[MIR] Fix CFI_INSTRUCTION escape printingScott Linder
2020-05-28[MachineVerifier] Verify that a DBG_VALUE has a debug locationVedant Kumar
2019-12-16[llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.Puyan Lotfi
2019-09-11[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet
2019-06-19Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault
2019-06-17[lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song
2018-10-01[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_RELReid Kleckner
2018-06-05[MIRParser] Add parser support for 'true' and 'false' i1s.Amara Emerson
2018-04-06[MIR] Add support for MachineFrameInfo::LocalFrameSizeFrancis Visoiu Mistrih
2017-07-07[RegAllocFast] Add the proper initialize method to use the .mir infrastructureQuentin Colombet
2017-06-29Remove redundant copy in recurrencesTaewook Oh
2017-06-06 Vivek Pandya
2017-06-06CodeGen: Refactor MIR parsingMatthias Braun
2017-06-02[RABasic] Properly initialize the passQuentin Colombet
2017-05-31TargetMachine: Indicate whether machine verifier passes.Matthias Braun
2017-05-24Move machine-cse-physreg.mir to test/CodeGen/ThumbKrzysztof Parzyszek
2017-05-24MachineCSE: Respect interblock physreg livenessMikael Holmen
2017-05-05MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun
2017-05-01MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFCMatthias Braun
2017-04-11MIR: Allow parsing of empty machine functionsJustin Bogner
2017-03-19Moving the test to x86 because other architectures do not suport regcall call...Oren Ben Simhon
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