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path: root/llvm/test/CodeGen/MIR/AMDGPU
AgeCommit message (Expand)Author
2025-09-03[AMDGPU] Remove most uses of /dev/null in tests (#156630)Jay Foad
2025-08-08[AMDGPU] AsmPrinter: Unify arg handling (#151672)Diana Picus
2025-07-29[AMDGPU] Add NoaliasAddrSpace to AAMDnodes (#149247)Shoreshen
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus
2025-07-15[AMDGPU] gfx1250 64-bit relocations and fixups (#148951)Stanislav Mekhanoshin
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus
2025-06-06[MIRParser] Report register class errors in a deterministic order (#142928)Jay Foad
2025-05-08[CodeGen] Parse nusw flag (#138856)Pierre van Houtryve
2025-04-15[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)Jun Wang
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus
2025-03-17AMDGPU: Migrate more tests away from undef (#131314)Matt Arsenault
2025-03-08[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)Shilei Tian
2025-01-23[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)Lucas Ramirez
2025-01-17[AMDGPU] Fix printing hasInitWholeWave in mir (#123232)Stanislav Mekhanoshin
2024-12-18[AMDGPU] Make max dwords of memory cluster configurable (#119342)Ruiling, Song
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-11-07Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)dyung
2024-11-07[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (#115291)Akshat Oke
2024-11-05[AMDGPU] Fix 3495d04 MIR test (#114963)Akshat Oke
2024-11-05[AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)Akshat Oke
2024-10-21Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)Akshat Oke
2024-10-15Revert "[AMDGPU] Serialize WWM_REG vreg flag (#110229)"Peter Collingbourne
2024-10-14[AMDGPU] Serialize WWM_REG vreg flag (#110229)Akshat Oke
2024-09-13Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)Diana Picus
2024-09-12Revert "Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)...Diana Picus
2024-09-12Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)" (#108173)Diana Picus
2024-09-10Revert "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)Vitaly Buka
2024-09-10[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic (#105822)Diana Picus
2024-09-05[AMDGPU] V_SET_INACTIVE optimizations (#98864)Carl Ritson
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-03-18[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)Jonas Paulsson
2024-02-09[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)Diana Picus
2024-02-05[CodeGen] Convert tests to opaque pointers (NFC)Nikita Popov
2024-01-18[AMDGPU] Add mark last scratch load pass (#75512)Mirko BrkuĊĦanin
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2023-11-30MachineVerifier: Reject extra non-register operands on instructions (#73758)Matt Arsenault
2023-08-21[AMDGPU] Add IsChainFunction to the MachineFunctionInfoDiana Picus
2023-08-20[GlobalISel] introduce MIFlag::NoConvergentSameer Sahasrabuddhe
2023-08-04[AMDGPU] Change syncscopes.mir not to use undefined cpol bits. NFC.Stanislav Mekhanoshin
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka
2023-07-21[Support] Implement LLVM_ENABLE_REVERSE_ITERATION for StringMapFangrui Song
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan
2023-06-29[AMDGPU] Reserve SGPR pair when long branches are presentBrendon Cahoon
2023-06-05[AMDGPU] Use resource base for buffer instruction MachineMemOperandsKrzysztof Drewniak
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