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path: root/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
AgeCommit message (Expand)Author
2024-03-18[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)Jonas Paulsson
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2022-06-01[AMDGPU][NFC] Refactor AMDGPUCallingConv.tdScott Linder
2022-03-09[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...Venkata Ramanaiah Nalamothu
2021-12-22Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to cal...Ron Lieberman
2021-12-22[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...RamNalamothu
2021-03-15[AMDGPU] Use single cache policy operandStanislav Mekhanoshin
2020-10-29[MIR] Fix out of bounds access in MIRPrinter.dfukalov
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