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path: root/llvm/test/CodeGen/ARM/misched-int-basic.mir
AgeCommit message (Expand)Author
2024-06-07[ARM] Add support for Cortex-R52+ (#94633)Jonathan Thackray
2019-09-11[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet
2018-09-26[CodeGen] Always print register ties in MI::dump()Francis Visoiu Mistrih
2018-01-31Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi
2018-01-18[CodeGen] Print RegClasses on MI in verbose modeFrancis Visoiu Mistrih
2018-01-09[CodeGen] Don't print "pred:" and "opt:" in -debug outputFrancis Visoiu Mistrih
2018-01-09[CodeGen] Don't print register classes in -debug outputFrancis Visoiu Mistrih
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
2017-05-25CodeGen: Rename DEBUG_TYPE to match passnamesMatthias Braun
2017-02-02[ARM] Classification Improvements to ARM Sched-Model. NFCI.Javed Absar