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path: root/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
AgeCommit message (Expand)Author
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David
2025-06-29[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)Guy David
2025-06-27[AMDGPU] Fix bad removal of s_delay_alu (#145728)Ana Mihajlovic
2025-04-23[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#13...Brox Chen
2025-04-22Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value ...zhijian lin
2025-04-21Revert "[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison valu...Nico Weber
2025-04-21[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in get...zhijian lin
2025-04-17Re apply 130577 narrow math for and operand (#133896)Shoreshen
2025-04-01Revert "[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable" ...Shoreshen
2025-04-01[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable (#130577)Shoreshen
2025-03-28[AMDGPU] Unused sdst writing to null (#133229)Ana Mihajlovic
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic
2025-02-24AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (#128388)Matt Arsenault
2025-02-22PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)Matt Arsenault
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov
2025-01-30PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)Matt Arsenault
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-11-05[AMDGPU] Extend type support for update_dpp intrinsic (#114597)Stanislav Mekhanoshin
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin
2024-10-07[AMDGPU] Only emit SCOPE_SYS global_wb (#110636)Pierre van Houtryve
2024-09-23AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)Matt Arsenault
2024-09-11[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)Jay Foad
2024-09-05[AMDGPU] V_SET_INACTIVE optimizations (#98864)Carl Ritson
2024-09-04[AMDGPU] Fix test update after #107108Jay Foad
2024-09-04[AMDGPU] Improve codegen for GFX10+ DPP reductions and scans (#107108)Jay Foad
2024-09-04[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)Carl Ritson
2024-07-26[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC)...Changpeng Fang
2024-07-23[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)Christudasan Devadasan
2024-07-16[AMDGPU] Implement GFX12 Memory Model (#98591)Pierre van Houtryve
2024-07-15[AMDGPU] Enable atomic optimizer for divergent i64 and double values (#96934)Vikram Hegde
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-07-08[AMDGPU] Cleanup bitcast spam in atomic optimizer (#96933)Vikram Hegde
2024-02-13[AMDGPU][SIMemoryLegalizer] Fix order of GL0/1_INV on GFX10/11 (#81450)Pierre van Houtryve
2024-01-18[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)Jay Foad
2024-01-17[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX12 (#77927)Jay Foad
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2024-01-08[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825)Jay Foad
2024-01-08[AMDGPU] Add new cache flushing instructions for GFX12 (#76944)Mirko Brkušanin
2023-12-25[LLVM] Make use of s_flbit_i32_b64 and s_ff1_i32_b64 (#75158)Acim Maravic
2023-12-15[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)Mirko Brkušanin
2023-12-15[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known t...Pierre van Houtryve
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad
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