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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
AgeCommit message (Expand)Author
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa
2025-07-03[RISCV] Use template version isInt<N> instead. NFC.Jim Lin
2025-07-03[RISCV] Add isel patterns for generating XAndesPerf branch immediate instruct...Jim Lin
2025-07-01[RISCV] Factor out getKillRegState in copyPhysReg (NFC) (#146454)Sudharsan Veeravalli
2025-06-27[RISCV] Add nds.bfos and nds.bfoz for the short forward branch optimization. ...Jim Lin
2025-06-25[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)Craig Topper
2025-06-25[RISCV] Explicitly check for supported opcodes in optimizeCondBranch. NFC (#1...Craig Topper
2025-06-25[RISCV] Remove -mattr=+no-rvc-hints (#145138)Craig Topper
2025-06-24[RISCV] Fix a correctness issue in optimizeCondBranch. Prevent optimizing com...Craig Topper
2025-06-23[RISCV][NFC] Remove hasStdExtCOrZca (#145139)Sam Elliott
2025-06-13[RISCV] Simplify macros used for commuting vector multiply-accumulate instruc...Craig Topper
2025-06-13[RISCV] Simplify macros used by RISCVInstrInfo::convertToThreeAddress. NFC (#...Craig Topper
2025-06-13[RISCV] Use RISCVII::getVecPolicyOpNum instead of making assumptions. NFC (#...Craig Topper
2025-06-13[RISCV] Use unsigned instead of uint16_t for the Opcode argument to getVector...Craig Topper
2025-06-12[RISCV] Remove implicit $vl def on vleNff pseudos (#143935)Luke Lau
2025-06-06[RISCV] Add missing immediate operand type for verifyInstruction. NFC. (#143056)Jim Lin
2025-05-30[RISCV] Use isVLPreservingConfig in isConvertibleToVMV_V_V. NFCCraig Topper
2025-05-29[RISCV] Canonicalize beq/bne with x0 as first arg to beqz/bnez (#141781)Alex Bradbury
2025-05-29[RISCV] Add bltu/bgeu zero => bnez/beqz canonicalisation to RISCVInstrInfo::s...Alex Bradbury
2025-05-28[RISCV] Use isVectorConfigInstr in isConvertibleToVMV_V_V. NFC (#141874)Craig Topper
2025-05-23[RISCV] Fix typo '==' instead of '='. NFCCraig Topper
2025-05-23[RISCV] Prevent using dummy_reg_pair_with_x0 in more places. (#141273)Craig Topper
2025-05-20[RISCV] Add LD_RV32/SD_RV32 to a few more functions in RISCVInstrInfo. (#140640)Craig Topper
2025-05-19[RISCV] Add LD_RV32/SD_RV32 to RISCVInstrInfo::canFoldIntoAddrMode. (#140631)Craig Topper
2025-05-17[RISCV] Use llvm::any_of (NFC) (#140398)Kazu Hirata
2025-05-16[RISCV] Add SEXT_INREG patterns for Xqcibm ext instruction (#140192)Sudharsan Veeravalli
2025-05-16[RISCV] Add isel patterns for generating Xqcibi branch instructions (#139872)Sudharsan Veeravalli
2025-05-15[RISCV] Use RISCVRegisterInfo::isRVVRegClass to replace IsScalableVector in s...Craig Topper
2025-05-09[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE...Craig Topper
2025-05-08[RISCV][TII] Add and use new hook to simplify/canonicalize instructions after...Alex Bradbury
2025-05-01[RISCV][NFC] Add missed // clang-format onAlex Bradbury
2025-04-30[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)Pengcheng Wang
2025-04-18[Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)Philip Reames
2025-04-17[RISCV] Move checking for constant 3/4 for XTHeadMemPair to the instruction m...Craig Topper
2025-04-16[RISCV] Add new CondCode COND_CV_BEQIMM/COND_CV_BNEIMM for CV immediate branc...Jim Lin
2025-04-08[RISCV] Add symbol parsing support for Xqcili load large immediate instructio...Sudharsan Veeravalli
2025-04-04[RISCV] Rename Spimm to StackAdj in most places. NFCCraig Topper
2025-03-28[RISCV] Add shift-add (SH1ADD, ...) to isCopyInstrImpl (#133443)Alex Bradbury
2025-03-28[RISCV] Add OR/XOR/SUB to RISCVInstrInfo::isCopyInstrImpl (#132002)Alex Bradbury
2025-03-27[RISCV][Xqccmp] Correctly Parse/Disassemble pushfp (#133188)Sam Elliott
2025-03-27[RISCV] Add late optimization pass for riscv (#133256)Mikhail R. Gadelha
2025-03-27[RISCV] Use TypeSize instead of uint64_t in getMachineMemOperand interface (#...Philip Reames
2025-03-27[RISCV] Canonicalize foldable branch conditions in optimizeCondBranch (#132988)Philip Reames
2025-03-26[RISCV] Use a precise size for MMO on scalable spill and fill (#133171)Philip Reames
2025-03-26[RISCV] Reduce control flow complexity in foldMemoryOperandImpl [nfc]Philip Reames
2025-03-25[RISCV][Xqcili] Implement Load Immediate Support (#132496)Sam Elliott
2025-03-21[RISCV] Introduce RISCV::RVVBytesPerBlock to simplify code [nfc] (#132436)Philip Reames
2025-03-21[RISCV] isLoadFromStackSlot and isStoreToStackSlot for vector spill/fill (#13...Philip Reames
2025-03-20[TTI] Use TypeSize in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#132244)Philip Reames
2025-03-19[RISCV] Add statistics for total LMUL spilled/reloaded (#131747)Luke Lau
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