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path: root/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
AgeCommit message (Expand)Author
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa
2025-07-03[RISCV] Add isel patterns for generating XAndesPerf branch immediate instruct...Jim Lin
2025-07-02[DAG] visitFREEZE - always allow freezing multiple operands (#145939)Simon Pilgrim
2025-06-30[ISel/RISCV] Fix fixed-vector [l]lrint lowering (#145898)Ramkumar Ramachandra
2025-06-28[ISel/RISCV] Refactor isPromotedOpNeedingSplit (NFC) (#146059)Ramkumar Ramachandra
2025-06-27[ISel/RISCV] Improve code in lowerFCOPYSIGN (NFC) (#146061)Ramkumar Ramachandra
2025-06-27[RISCV] Simplify the check for when to call EmitLoweredCascadedSelect. NFC (#...Craig Topper
2025-06-27[RISCV] Add ISel patterns for Qualcomm uC Xqcicm extension (#145643)quic_hchandel
2025-06-25[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)Craig Topper
2025-06-25[RISCV] Support fixed vector vp.reverse/splice with Zvfhmin/Zvfbfmin. (#145596)Craig Topper
2025-06-25[RISCV] Try to optimize `vp.splice` to `vslide1up`. (#144871)Ming Yan
2025-06-24[RISCV] Support scalable vector vp.reverse/splice with Zvfhmin/Zvfbfmin. (#14...Craig Topper
2025-06-24[RISCV] Optimize vp.splice with 0 offset. (#145533)Craig Topper
2025-06-24[RISCV] Support LLVM IR intrinsics for XAndesVBFHCvt (#145321)Jim Lin
2025-06-24[RISCV] Add ISel pattern for generating QC_BREV32 (#145288)Sudharsan Veeravalli
2025-06-23[RISCV][NFC] Remove hasStdExtCOrZca (#145139)Sam Elliott
2025-06-23CodeGen: Emit error if getRegisterByName fails (#145194)Matt Arsenault
2025-06-21Re-commit "[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoa...Craig Topper
2025-06-21Revert "[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. ...Craig Topper
2025-06-21[RISCV] Properly support RISCVISD::LLA in getTargetConstantFromLoad. (#145112)Craig Topper
2025-06-20[RISCV] Allow larger offset when matching build_vector as vid sequence (#144756)Philip Reames
2025-06-20[RISCV] Treat bf16->f32 as separate ExtKind in combineOp_VLToVWOp_VL. (#144653)Craig Topper
2025-06-18[RISCV] Support non-power-of-2 types when expanding memcmpPengcheng Wang
2025-06-17[RISCV] Set the exact flag on the SRL created for converting vscale to a read...Craig Topper
2025-06-17[RISCV] Consolidate both copies of getLMUL1VT [nfc] (#144568)Philip Reames
2025-06-16[RISCV] Use RISCV::RVVBitsPerBlock instead of 64 in getLMUL1VT. NFC (#144401)Craig Topper
2025-06-13[RISCV] Lower SELECT's with one constant more efficiently using Zicond (#143581)Ryan Buchner
2025-06-13[RISCV] Support memcmp expansion for vectorsPengcheng Wang
2025-06-11[RISCV][FPEnv] Lowering of fpenv intrinsics (#141498)Serge Pavlov
2025-06-10[RISCV] Remove the TODO for vqdotsu. NFC.Jim Lin
2025-06-10[RISCV] Don't select sh{1,2,3}add if shl doesn't have one use (#143351)Jim Lin
2025-06-09[RISCV] Migrate zvqdotq reduce matching to use partial_reduce infrastructure ...Philip Reames
2025-06-09[SDAG] Add partial_reduce_sumla node (#141267)Philip Reames
2025-06-07[RISC-V] Adjust trampoline code for branch control flow protection (#141949)Jesse Huang
2025-06-06[RISCV] Don't commute with shift if XAndesPerf is enabled (#142920)Jim Lin
2025-06-03[RISCV] Optimize two source deinterleave2 via ri.vunzip2{a,b} (#142667)Philip Reames
2025-06-03[RISCV][NFC] Simplify ISD::SELECT Legality (#142650)Sam Elliott
2025-06-03[RISCV] Use ri.vunzip2{a,b} for e64 fixed length deinterleave(2) shuffles (#1...Philip Reames
2025-05-30[RISCV] Use llvm::is_contained. NFC (#142239)Craig Topper
2025-05-30[RISCV] Fix a warningKazu Hirata
2025-05-30[RISCV] Fix a bug in partial.reduce lowering for zvqdotq .vx forms (#142185)Philip Reames
2025-05-29[SDAG] Split the partial reduce legalize table by opcode [nfc] (#141970)Philip Reames
2025-05-29[RISCV] Add ORC_B to SimplifyDemandedBitsForTargetNode. (#141975)Craig Topper
2025-05-29[RISCV] Custom type legalize MVT::i8 BITREVERSE to BREV8. (#142001)Craig Topper
2025-05-29[RISCV] Add BREV8 to SimplifyDemandedBitsForTargetNode. (#141898)Craig Topper
2025-05-29[SDAG] Make Select-with-Identity-Fold More Flexible; NFC (#136554)Marius Kamp
2025-05-23[RISCV] Custom lower fixed length partial.reduce to zvqdotq (#141180)Philip Reames
2025-05-23[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)Rahul Joshi
2025-05-23[RISC-V] Allow intrinsics to be used with any pointer type. (#139634)Harald van Dijk
2025-05-22[RISCV] Lower PARTIAL_REDUCE_[S/U]MLA via zvqdotq (#140950)Philip Reames
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