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path: root/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
AgeCommit message (Expand)Author
2025-09-10[RISCV] Add helper method for detecting BEXTI or TH_TST is supported. NFC (#1...Craig Topper
2025-09-09[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#1...Craig Topper
2025-09-05[RISCV] Add th.ext(u) to RISCVDAGToDAGISel::hasAllNBitUsers. (#157133)Craig Topper
2025-09-03[RISCV] Add changes to have better coverage for qc.insb and qc.insbi (#154135)quic_hchandel
2025-08-19[RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (#154023)Sudharsan Veeravalli
2025-08-19[RISCV] Use sd_match in trySignedBitfieldInsertInMask (#154152)Sudharsan Veeravalli
2025-08-18[RISCV] Prioritize zext.h/zext.w over XTheadBb th.extu. (#154186)Craig Topper
2025-08-14[RISCV] Add CodeGen support for qc.insbi and qc.insb insert instructions (#15...quic_hchandel
2025-07-31[RISCV] Add RISCVISD::LD_RV32/SD_RV32 to isWorthFoldingAdd. (#151606)Craig Topper
2025-07-30[RISCV] Handled the uimm9 offset while FrameIndex folding. (#149303)UmeshKalappa
2025-07-29[RISCV] Use SDValue::getOperand instead of SDNode::getOperand for consistency...Craig Topper
2025-07-22[RISCV] Add profitability checks to SelectAddrRegRegScale. (#150135)Craig Topper
2025-07-19[RISCV] Add a non-template version of SelectAddrRegZextRegScale and move code...Craig Topper
2025-07-17[RISCV] Teach SelectAddrRegRegScale that ADD is commutable. (#149231)Craig Topper
2025-07-15[RISCV] Refactor SelectAddrRegRegScale. NFCCraig Topper
2025-07-15[RISCV] Remove duplicate check in an if statement. NFCCraig Topper
2025-07-15[RISCV] Simplify conversion from ISD::Constant to ISD::TargetConstant in Sele...Craig Topper
2025-07-15[RISCV] Add early out to reduce indentation in SelectAddrRegRegScale. NFCCraig Topper
2025-07-15[RISCV] Fix issues in ORI to QC.INSBI transformation (#148809)Sudharsan Veeravalli
2025-07-15[RISCV] Remove incorrect and untested FrameIndex support from SelectAddrRegIm...Craig Topper
2025-07-14[RISCV] Move RISCVDAGToDAGISel::SelectAddrRegRegScale definition later. NFCCraig Topper
2025-07-14[RISCV] Fix typo in comment. NFC (#148754)Craig Topper
2025-07-14[RISCV] Refactor RISCVDAGToDAGISel::selectSimm5Shl2. NFC (#148731)Craig Topper
2025-07-11[RISCV] Add riscv_vlm/vsm to RISCVTargetLowering::getTgtMemIntrinsic. (#148265)Craig Topper
2025-07-09[RISCV] Use Selection::haveNoCommonBitsSet in RISCVDAGToDAGISel::orDisjoint. ...Craig Topper
2025-07-09[RISCV] Support LLVM IR intrinsics for XAndesVSIntLoad (#147493)Jim Lin
2025-07-08[RISCV] Select disjoint_or+not as xnor. (#147636)Craig Topper
2025-07-08[RISCV] Use cast instead of dyn_cast to MemSDNode in RISCVISelDAGToDAG.cpp. (...Craig Topper
2025-07-08[RISCV] Use QC.INSBI for OR with immediate when ORI isn't possible (#147349)Sudharsan Veeravalli
2025-07-04[RISCV] Move performCombineVMergeAndVOps to RISCVVectorPeephole (#144076)Luke Lau
2025-07-03[RISCV] Add SF_ to SiFive instructions in RISCVGenInstrInfo.inc. NFC (#146939)Craig Topper
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa
2025-06-27[RISCV] Remove untested code from SelectAddrRegRegScale. (#146185)Craig Topper
2025-06-11[RISCV] Select signed bitfield insert for XAndesPerf (#143356)Jim Lin
2025-06-10[RISCV] Select signed bitfield extract for Xqcibm (#143536)Sudharsan Veeravalli
2025-06-10[RISCV] Select (add/or C, x) -> (add.uw C|0xffffffff00000000, x) (#143375)Piotr Fusik
2025-06-10[RISCV] Select unsigned bitfield extract for Xqcibm (#143354)Sudharsan Veeravalli
2025-06-09[RISCV] Pass SDLoc by const reference. NFCCraig Topper
2025-06-06[RISCV] Select unsigned bitfield insert for XAndesPerf (#142737)Jim Lin
2025-06-05[RISCV] Remove artificial restriction on ShAmt from (shl (and X, C2), C) -> (...Craig Topper
2025-06-04[RISCV] Fold SRLIW+SLLI+ADD into SRLIW+SHXADD (#142611)Piotr Fusik
2025-06-03[RISCV] Select signed bitfield extracts for XAndesPerf (#142303)Jim Lin
2025-05-29[RISCV] Select unsigned bitfield extracts for XAndesPerf (#141398)Jim Lin
2025-05-28[RISCV] Use X0_Pair for storing 0 using Zilsd. (#141847)Craig Topper
2025-05-27[RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)Craig Topper
2025-05-15[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA....Craig Topper
2025-05-14[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)Craig Topper
2025-05-13[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)Piotr Fusik
2025-05-13[RISCV] Use QC_E_ADDI to improve codegen for icmp {eq, ne} with a constant (#...Sudharsan Veeravalli
2025-05-09[RISCV] TableGen-erate RISC-V SDNodes (#138381)Sam Elliott
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