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path: root/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
AgeCommit message (Expand)Author
2024-06-17[RISCV] Remove getOffsetOfLocalArea() (#93765)Pengcheng Wang
2024-05-14[RISCV] Add X27 to SavedRegs when X26 is in SavedRegs for cm.push/pop (#92067)Craig Topper
2024-05-13[RISCV] Remove AllPopRegs array from RISCVFrameLowering.cpp. NFCCraig Topper
2024-04-17[RISCV] Add CFI information for vector callee-saved registers (#86811)Brandon Wu
2024-04-10[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determ...Craig Topper
2024-03-27[RISCV] RISCV vector calling convention (1/2) (#77560)Brandon Wu
2024-03-26[RISCV] Align stack size down to a multiple of 16 before using cm.push/pop. (...Craig Topper
2024-02-20[RISCV] Add a query for exact VLEN to RISCVSubtarget [nfc]Philip Reames
2024-02-13[RISCV] Register fixed stack slots for callee saved registers for -msave-rest...Craig Topper
2024-02-10[RISCV] Add Zicfiss support to the shadow call stack implementation. (#68075)Yeting Kuo
2024-02-09[RISCV] Lower the TransientStackAlignment to the ABI alignment for rv32e/rv64e.Craig Topper
2024-02-09[RISCV] Remove unnecessary check for RVE from determineCalleeSaves. NFCICraig Topper
2024-02-08[RISCV] Use MCPhysReg for AllPopRegs. NFCCraig Topper
2024-02-06[RISCV] Remove CalleeSavedInfo for Zcmp/save-restore-libcalls registers (#79535)Visoiu Mistrih Francis
2024-02-06[RISCV] Use hasStdExtCOrZca instead of hasStdExtC in estimateFunctionSizeInBy...Craig Topper
2024-01-16[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)Wang Pengcheng
2023-12-01[RISCV] Remove null terminator from CSRegs in determineCalleeSaves. NFC (#74131)Craig Topper
2023-11-17[RISCV] Fix crash in PEI with empty entry block with Zcmp (#72117)Nemanja Ivanovic
2023-09-25[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)Yeting Kuo
2023-09-20[RISCV] Fix bugs about register list of Zcmp push/pop. (#66073)Yeting Kuo
2023-09-19[RISCV][NFC] Simplify the sp-offset reduction by spimm of CM.PUSH/POP. (#66667)Yeting Kuo
2023-09-06[RISCV] Adjust first sp size to use c.addi16sp.laichunfeng
2023-08-29[RISCV] Fix assertion failure when zcmp extension is enabled.Garvit Gupta
2023-08-18[RISCV] Compress stack insts by adjust offset.laichunfeng
2023-08-07[RISCV] Refine getMaxPushPopReg like getLibCallID. NFC.Jim Lin
2023-08-03[RISCV] Use max pushed register to get pushed register number.Yeting Kuo
2023-08-02[RISCV] Fix the CFI offset for callee-saved registers stored by Zcmp push.Jim Lin
2023-07-26[RISCV] Reuse FrameIdx for emitting cfi offset. NFC.Jim Lin
2023-07-07[RISCV] Readjusting the framestack for ZcmpWuXinlong
2023-06-26[MC] Add SMLoc to MCCFIInstructionFangrui Song
2023-04-26[RISCV] Make SCS prologue interrupt safe on RISC-VPaul Kirth
2023-04-12[CodeGen][RISCV] Change Shadow Call Stack Register to X3Paul Kirth
2023-03-27[RISCV] Replace RISCV -> RISC-V in comments. NFCCraig Topper
2023-03-15[codegen][riscv] Emit CFI directives when using shadow call stackPaul Kirth
2022-12-17[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStac...Christudasan Devadasan
2022-12-06[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustmentSergey Kachkov
2022-11-30[RISCV] Inline RISCVFrameLowering::adjustReg out of existance [nfc]Philip Reames
2022-11-30[RISCV] Adjust code to fallthrough to a single adjustReg callsite [nfc]Philip Reames
2022-11-30[RISCV] Merge two versions of adjustReg on TRI [nfc]Philip Reames
2022-11-30[RISCV] Reuse and generalize adjustReg from another spot in frame lowering [nfc]Philip Reames
2022-11-30[RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer con...Philip Reames
2022-11-28[RISCV] Move implementation of adjustReg from frame lowering to register info...Philip Reames
2022-11-18[RISCV] Optimize scalable frame setup when VLEN is precisely knownPhilip Reames
2022-10-20[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with ...Craig Topper
2022-10-03[RISCV] Pass the destination register to getVLENFactoredAmount instead of ret...Craig Topper
2022-08-24[RISCV] Handle register spill in branch relaxationZHU Zijia
2022-08-14Use llvm::none_of (NFC)Kazu Hirata
2022-08-02[RISCV][NFCI] Set TransientStackAlignment and rely on it rather than RVV-spec...Alex Bradbury
2022-07-13[RISCV] Add early-exit to RVV stack computation. NFCI.Fraser Cormack
2022-07-03[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offsetluxufan
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