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path: root/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
AgeCommit message (Expand)Author
2025-02-24[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister....Craig Topper
2025-01-22[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (N...Venkata Ramanaiah Nalamothu
2024-11-12[ARM] Remove unused includes (NFC) (#115995)Kazu Hirata
2024-10-09[ARM] Honour -mno-movt in stack protector handling (#109022)Ard Biesheuvel
2024-08-27[TII][RISCV] Add renamable bit to copyPhysReg (#91179)Piyou Chen
2024-06-28[IR] Don't include Module.h in Analysis.h (NFC) (#97023)Nikita Popov
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang
2024-04-15[ARM][Thumb2] Mark BTI-clearing instructions as scheduling region boundaries ...Victor Campos
2024-04-04Revert "[ARM][Thumb2] Mark BTI-clearing instructions as scheduling region bou...Victor Campos
2024-04-04[ARM][Thumb2] Mark BTI-clearing instructions as scheduling region boundaries ...Victor Campos
2024-01-22[Thumb,ELF] Fix access to dso_preemptable __stack_chk_guard with static reloc...Fangrui Song
2023-02-13[ARM] Use llvm::rotl and llvm::rotr (NFC)Kazu Hirata
2023-01-28[Target] Use llvm::count{l,r}_{zero,one} (NFC)Kazu Hirata
2023-01-23[MC] Make more use of MCInstrDesc::operands. NFC.Jay Foad
2023-01-13[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegist...Craig Topper
2022-12-17[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStac...Christudasan Devadasan
2022-03-16[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated ...Shengchen Kan
2021-12-02[ARM] Introduce i8neg and i8pos addressing modesDavid Green
2021-11-30[ARM] create new pseudo t2LDRLIT_ga_pcrel for stack guardsNick Desaulniers
2021-11-09[ARM] implement support for TLS register based stack protectorArd Biesheuvel
2021-11-08[ARM] implement LOAD_STACK_GUARD for remaining targetsArd Biesheuvel
2021-09-28[ARM] Skip debug info in recomputeVPTBlockMaskDavid Green
2021-03-15Change void getNoop(MCInst &NopInst) to MCInst getNop()Fangrui Song
2020-08-13[ARM] Mark VMINNMA/VMAXNMA as commutativeDavid Green
2020-07-16[ARM] Add a PreferNoCSEL option. NFCDavid Green
2020-07-16[ARM] CSEL generationDavid Green
2020-05-27[ARM] Fix rewrite of frame index in Thumb2's address mode i8s4Victor Campos
2020-05-12Fold single-use variables into assertBenjamin Kramer
2020-05-12[Target][ARM] Replace outdated getARMVPTBlockMask functionPierre-vh
2020-04-07CodeGen: More conversions to use RegisterMatt Arsenault
2020-03-31[Alignment][NFC] Transitionning more getMachineMemOperand call sitesGuillaume Chatelet
2020-02-03[NFC] unsigned->Register in storeRegTo/loadRegFromStackSimon Moll
2020-01-14[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio
2020-01-10Reverting, broke some bots. Need further investigation.Diogo Sampaio
2020-01-10[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio
2019-12-30[ARM][THUMB2] Allow emitting T3 types of add and subDiogo Sampaio
2019-11-14ARM: allow rewriting frame indexes for all prefetch variants.Tim Northover
2019-11-11Use MCRegister in copyPhysRegMatt Arsenault
2019-10-28[ARM][Thumb2InstrInfo] Fix default `0` opcode when rewriting frame indicesDavid Tellenbach
2019-10-16[ARM] Add a register class for GPR pairs without SP and use it. NFCIMikhail Maltsev
2019-08-16[ARM] Correct register for narrowing and widening MVE loads and stores.David Green
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders
2019-06-25[ARM] Add MVE vector load/store instructions.Simon Tatham
2019-06-14[ARM] MVE VPT Block PassSjoerd Meijer
2019-06-11[ARM] Fix unused-variable warning in rL363039.Simon Tatham
2019-06-11[ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham
2019-06-10Revert rL362953 and its followup rL362955.Simon Tatham
2019-06-10[ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham
2019-05-24[ARM] additionally check for ARM::INLINEASM_BR w/ ARM::INLINEASMNick Desaulniers
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