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path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
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2022-02-06[llvm] Use = default (NFC)Kazu Hirata
2022-01-06[Target] Remove redundant member initialization (NFC)Kazu Hirata
Identified with readability-redundant-member-init.
2022-01-03Revert "[llvm] Remove redundant member initialization (NFC)"Kazu Hirata
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3. This patch causes gcc to issue a lot of warnings like: warning: base class ‘class llvm::MCParsedAsmOperand’ should be explicitly initialized in the copy constructor [-Wextra]
2022-01-01[llvm] Remove redundant member initialization (NFC)Kazu Hirata
Identified with readability-redundant-member-init.
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2015-03-12Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher
classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010
2014-03-22Prune includes in ARM target.Craig Topper
llvm-svn: 204548
2013-06-07Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling
the internals of TargetMachine could change. llvm-svn: 183488
2012-03-17Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper
llvm-svn: 152978
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu
MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2011-12-20Unweaken vtables as per ↵David Blaikie
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
2011-04-18Trim a few unneeded includes.Jim Grosbach
llvm-svn: 129723
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov
and fixes here and there. llvm-svn: 123170
2009-07-08Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin
llvm-svn: 75036
2009-07-08Push methods into base class in preparation for sharing.David Goodwin
llvm-svn: 75020
2009-07-08Start converting to new error handling API.Torok Edwin
cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) llvm-svn: 75018
2009-07-08Start breaking out common base functionality for register info.David Goodwin
llvm-svn: 75016
2009-07-01Fix a comment typo.Bob Wilson
llvm-svn: 74650
2009-06-27Simplify a bitAnton Korobeynikov
llvm-svn: 74385
2009-06-27ARM refactoring. Step 2: split RegisterInfoAnton Korobeynikov
llvm-svn: 74384
2009-06-22For Darwin on ARMv6 and newer, make register r9 available for use as aBob Wilson
caller-saved register. llvm-svn: 73901
2009-06-22hasFP should return true if frame address is taken.Evan Cheng
llvm-svn: 73893
2009-06-18Remove UseThumbBacktraces. Just check if subtarget is darwin.Evan Cheng
llvm-svn: 73734
2009-06-18- Update register allocation hint after coalescing. This is done by the ↵Evan Cheng
target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. llvm-svn: 73671
2009-06-15On Darwin, frame pointer r7 is never available.Evan Cheng
llvm-svn: 73434
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
2009-05-30Untabification.Bill Wendling
llvm-svn: 72604
2009-05-19Follow up on new support for memory operands in ARM inline assembly.Bob Wilson
This fixes pr4233. llvm-svn: 72115
2009-05-13Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling
booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
2009-04-07PR2985 / <rdar://problem/6584986>Jim Grosbach
When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. llvm-svn: 68545
2009-03-13Fix some significant problems with constant pools that resulted in ↵Evan Cheng
unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
2009-02-23Propagate debug loc info through prologue/epilogue.Bill Wendling
llvm-svn: 65298
2009-02-13and one more fileDale Johannesen
llvm-svn: 64430
2009-02-06Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng
llvm-svn: 63938
2008-12-10Preliminary ARM debug support based on patch by Mikael of FlexyCore.Evan Cheng
llvm-svn: 60851
2008-12-03Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman
is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. llvm-svn: 60459
2008-11-12Fix encoding of single-precision VFP registers.Evan Cheng
llvm-svn: 59102
2008-10-03Switch the MachineOperand accessors back to the short names likeDan Gohman
isReg, etc., from isRegister, etc. llvm-svn: 57006
2008-09-27Re-apply 56683 with fixes.Evan Cheng
llvm-svn: 56748
2008-09-26Temporarily reverting r56683. This is causing a failure during the build of ↵Bill Wendling
llvm-gcc: /Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311. ../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. {standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" {standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression {standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" ... llvm-svn: 56703
2008-09-26Fix @llvm.frameaddress codegen. FP elimination optimization should be ↵Evan Cheng
disabled when frame address is desired. Also add support for depth > 0. llvm-svn: 56683
2008-04-16Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray
instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
2008-03-31Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng
llvm-svn: 48995
2008-02-27Spiller now remove unused spill slots.Evan Cheng
llvm-svn: 47657
2008-02-20Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov
llvm-svn: 47369
2008-02-10Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman
llvm-svn: 46930
2008-01-11rename MachineInstr::setInstrDescriptor -> setDescChris Lattner
llvm-svn: 45871
2008-01-07rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner
Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
2008-01-07Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner
that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
2008-01-07Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson
Some day I'll get it all moved over... llvm-svn: 45672
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