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path: root/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
AgeCommit message (Expand)Author
2025-09-05[AMDGPU] Prevent VOPD combining of VGPRs with different MSBs (#157168)Stanislav Mekhanoshin
2025-09-04[AMDGPU] High VGPR lowering on gfx1250 (#156965)Stanislav Mekhanoshin
2025-09-04[AMDGPU] Ensure positive InstOffset for buffer operations (#145504)Aleksandar Spasojevic
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin
2025-09-03AMDGPU: Refactor isImmOperandLegal (#155607)Matt Arsenault
2025-09-02[AMDGPU] Adjust VGPR allocation encoding on gfx1250 (#156546)Stanislav Mekhanoshin
2025-08-22[AMDGPU] Common up two local memory size calculations. NFCI. (#154784)Jay Foad
2025-08-19[AMDGPU] Check noalias.addrspace in mayAccessScratchThroughFlat (#151319)Pierre van Houtryve
2025-08-18[AMDGPU] User SGPR count increased to 32 on gfx1250 (#154205)Stanislav Mekhanoshin
2025-08-14[AMDGPU] Don't allow wgp mode on gfx1250 (#153680)Stanislav Mekhanoshin
2025-08-14[AMDGPU] Increase LDS to 320K on gfx1250 (#153645)Stanislav Mekhanoshin
2025-08-11[AMDGPU] Per-subtarget DPP instruction classification (#153096)Stanislav Mekhanoshin
2025-08-07[AMDGPU] Restrict packed math FP32 instructions to read only one SGPR per ope...Stanislav Mekhanoshin
2025-08-05[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203)Stanislav Mekhanoshin
2025-08-01AMDGPU: Move asm constraint physreg parsing to utils (#150903)Matt Arsenault
2025-07-30[AMDGPU] Add v_cvt_sr|pk_bf8|fp8_f16 gfx1250 instructions (#151415)Stanislav Mekhanoshin
2025-07-28[AMDGPU] MC support for async load and store on gfx1250 (#151030)Changpeng Fang
2025-07-21[AMDGPU] MC support for gfx1250 scale_offset modifier (#149881)Stanislav Mekhanoshin
2025-07-21AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)Changpeng Fang
2025-07-16AMDGPU: Treat WMMA XDL ops as TRANS in S_DELAY_ALU insertion for gfx1250 (#14...Changpeng Fang
2025-07-14[AMDGPU] Add gfx1250 v_fmac_f64 implementation (#148725)Stanislav Mekhanoshin
2025-07-10[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)Stanislav Mekhanoshin
2025-07-09[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)Stanislav Mekhanoshin
2025-07-03AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)Changpeng Fang
2025-06-25[AMDGPU][GFX1250] Insert S_WAIT_XCNT for SMEM and VMEM load-stores (#145566)Christudasan Devadasan
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus
2025-06-21[AMDGPU] Rename call instructions from b64 to i64 (#145103)Stanislav Mekhanoshin
2025-06-05[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)Diana Picus
2025-05-14[AMDGPU] Use std::optional::value_or (NFC) (#140006)Kazu Hirata
2025-05-13Reapply "[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during sched...Lucas Ramirez
2025-05-09Revert "[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during schedu...Vitaly Buka
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev
2025-05-08[AMDGPU][NFC] Remove unused operand types. (#139062)Ivan Kosarev
2025-05-08[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during scheduling (#1...Lucas Ramirez
2025-04-13[AMDGPU][True16][MC] fix fmac_f16_t16 vop3 format (#135464)Brox Chen
2025-03-29[NFC][AMDGPU] clang-format `AMDGPUBaseInfo.[h,cpp]` (#133559)Shilei Tian
2025-03-27[AMDGPU] Add a new function `getIntegerPairAttribute` (#133271)Shilei Tian
2025-03-21Reapply "[AMDGPU] Use COV6 by default (#118515)" (#130963)Shilei Tian
2025-03-19[AMDGPU] Update target helpers & GCNSchedStrategy for dynamic VGPRs (#130047)Diana Picus
2025-03-17[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)Alex Voicu
2025-03-14[NFC][AMDGPU] Replace more direct arch comparison with isAMDGCN() (#131379)Shilei Tian
2025-03-12[AMDGPU] Merge consecutive wait_alu instruction (#128916)Ana Mihajlovic
2025-03-03[AMDGPU] Simplify conditional expressions. NFC. (#129228)Jay Foad
2025-02-25[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)Brox Chen
2025-02-18[AMDGPU][True16][CodeGen] reopen "FLAT_load using D16 pseudo instruction" (#1...Brox Chen
2025-02-18Revert "[AMDGPU][True16][CodeGen] FLAT_load using D16 pseudo instruction (#11...Nikita Popov
2025-02-18[AMDGPU][True16][CodeGen] FLAT_load using D16 pseudo instruction (#114500)Brox Chen
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson
2025-01-22[AMDGPU] Fix unreachable reg bit width (#122107)Shoreshen
2024-12-11[AMDGPU][Attributor] Make `AAAMDFlatWorkGroupSize` honor existing attribute (...Shilei Tian
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