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path: root/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
AgeCommit message (Expand)Author
2025-08-22[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)Ivan Kosarev
2025-08-12[llvm] Support multiple save/restore points in mir (#119357)Elizaveta Noskova
2025-07-28AMDGPU: Move getMaxNumVectorRegs into GCNSubtarget (NFC) (#150889)Matt Arsenault
2025-07-28AMDGPU: Avoid contraction in wwm allocation failure message (#150888)Matt Arsenault
2025-05-23[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)Rahul Joshi
2025-04-25[AMDGPU] Remove unused variables in SILowerSGPRSpills.cpp (NFC)Jie Fu
2025-04-25Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)Diana Picus
2025-03-18[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator ...Vikash Gupta
2024-12-17AMDGPU: Delete spills of undef values (#119684)Matt Arsenault
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata
2024-10-22[AMDGPU] Correct pass dependencies for SILowerSGPRSpills (#109937)Akshat Oke
2024-10-22[NewPM][CodeGen] Port VirtRegMap to NPM (#109936)Akshat Oke
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan
2024-09-24[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. ...Pravin Jagtap
2024-09-21[AMDGPU][NewPM] Port SILowerSGPRSpills to NPM (#108934)Akshat Oke
2024-07-17[AMDGPU] clang-tidy: use emplace_back instead of push_back. NFC.Jay Foad
2024-07-10[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)paperchalice
2024-07-09[CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941)paperchalice
2024-04-18[AMDGPU] Fix end() iterator dereference in SILowerSGPRSpills (#88828)bcahoon
2024-01-24[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)Christudasan Devadasan
2024-01-23[AMDGPU] SILowerSGPRSpills: do not update MRI reserve registers (#77888)Carl Ritson
2023-09-29[AMDGPU] Introduce AMDGPU::SGPR_SPILL asm comment flag (#67091)Yashwant Singh
2023-09-22[llvm] Use llvm::is_contained (NFC)Kazu Hirata
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2022-12-17[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStac...Christudasan Devadasan
2022-12-17[AMDGPU] Separate out SGPR spills to VGPR lanes during PEIChristudasan Devadasan
2022-12-17[AMDGPU] Callee must always spill writelane VGPRsChristudasan Devadasan
2022-11-04[AMDGPU] Skip stack-arg dbg objects while fixing the dead frame indicesChristudasan Devadasan
2022-10-07AMDGPU: Update SlotIndexes independently of LiveIntervalsMatt Arsenault
2022-07-05[NFC] Fix wrong comment.Thomas Symalla
2022-03-16Cleanup codegen includesserge-sans-paille
2022-03-10Revert "Cleanup codegen includes"Nico Weber
2022-03-10Cleanup codegen includesserge-sans-paille
2022-03-09[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...Venkata Ramanaiah Nalamothu
2022-02-02AMDGPU: Add second emergency slot for SGPR to vmem for large framesMatt Arsenault
2022-01-19[NFC] Use Register instead of unsignedJim Lin
2022-01-11[AMDGPU] Do not reserve any VGPR for SGPR spillsAustin Kerbow
2021-12-22Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to cal...Ron Lieberman
2021-12-22[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...RamNalamothu
2021-11-12[AMDGPU][NFC] Fix typosNeubauer, Sebastian
2021-11-03[AArch64, AMDGPU] Use make_early_inc_range (NFC)Kazu Hirata
2021-10-18[AMDGPU] Remove unused VirtRegMap analysis. NFC.Jay Foad
2021-10-12[AMDGPU] Remove dead frame indices after sgpr spill.hsmahesha
2021-10-07[MachineInstr] Move MIParser's DBG_VALUE RegState::Debug invariant into Machi...Jack Andersen
2021-07-13RegAlloc: Allow targets to split register allocationMatt Arsenault
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