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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
AgeCommit message (Expand)Author
2025-07-01AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive...Changpeng Fang
2025-06-26AMDGPU: Avoid report_fatal_error for unsupported ds_ordered_count (#145172)Matt Arsenault
2025-06-24[AMDGPU][True16][CodeGen] do not legalize t16 operand during user scan (#145450)Brox Chen
2025-06-22[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (#145152)Stanislav Mekhanoshin
2025-06-19[AMDGPU][True16][Codegen] keep srcmod/clamp/omod from v_s_xxx_f16 when moved ...Brox Chen
2025-06-10[AMDGPU][True16][CodeGen] v_s_xxx_f16 t16 mode handling in movetoVALU process...Brox Chen
2025-06-05[AMDGPU] Move S_ADD_U64_PSEUDO handling into getVALUOp. NFC. (#142934)Jay Foad
2025-06-04[AMDGPU][True16][CodeGen] legalize 16bit and 32bit use-def chain for moveToVA...Brox Chen
2025-05-29AMDGPU: Remove redundant operand folding checks (#140587)Matt Arsenault
2025-05-28Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)Justin Bogner
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev
2025-05-08[AMDGPU][NFC] Remove unused operand types. (#139062)Ivan Kosarev
2025-05-07[AMDGPU][True16][CodeGen] replace subreg_to_reg to req_sequence (#138746)Brox Chen
2025-04-22[AMDGPU] SIInstrInfo: Fix resultDependsOnExec for VOPC instructions (#134629)Frederik Harwath
2025-04-18[Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)Philip Reames
2025-04-03[AMDGPU][True16][CodeGen] legalize operands when move16bit SALU to VALU (#133...Brox Chen
2025-04-01[AMDGPU][True16][CodeGen] fix moveToVALU with proper subreg access in true16 ...Brox Chen
2025-03-21[AMDGPU] Insert before and after instructions that always use GDS (#131338)Stephen Thomas
2025-03-14[NFC][AMDGPU] Replace multiple calls to `MI.getOpcode()` with `Opcode` (#131400)Shilei Tian
2025-03-12[AMDGPU] Ignore RegMask operands when folding operands to SALU insts (#130813)Mirko Brkušanin
2025-03-07AMDGPU: Add pseudoinstruction for agpr or vgpr constants (#130042)Matt Arsenault
2025-03-04AMDGPU: Use const reference for DebugLocMatt Arsenault
2025-02-28[AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. (#129103)sstipano
2025-02-27[AMDGPU] Verify SdwaSel value range (#128898)Frederik Harwath
2025-02-26[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)Brox Chen
2025-02-26[AMDGPU][True16][CodeGen] true16 codegen for valu op (#124797)Brox Chen
2025-02-26[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)Pierre van Houtryve
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve
2025-02-24[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister....Craig Topper
2025-02-19[AMDGPU] Remove unused variables. NFCBenjamin Kramer
2025-02-19[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)Brox Chen
2025-02-19AMDGPU: Teach isOperandLegal about SALU literal restrictions (#127626)Matt Arsenault
2025-02-18AMDGPU: Correct legal literal operand logic for multiple uses (#127594)Matt Arsenault
2025-02-18AMDGPU: Extract lambda used in foldImmediate into a helper function (#127484)Matt Arsenault
2025-02-18AMDGPU: Handle brev and not cases in getConstValDefinedInReg (#127483)Matt Arsenault
2025-02-18AMDGPU: Implement getConstValDefinedInReg and use in foldImmediate (NFC) (#12...Matt Arsenault
2025-02-18AMDGPU: Fix foldImmediate breaking register class constraints (#127481)Matt Arsenault
2025-02-16[AMDGPU] Remove materializeImmediate (#127420)Kazu Hirata
2025-02-14Revert "[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#12… (#12...Brox Chen
2025-02-14[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#122950)Brox Chen
2025-02-12[TableGen] Emit OpName as an enum class instead of a namespace (#125313)Rahul Joshi
2025-01-30[amdgpu][nfc] Post-commit feedback on c39fba209Jon Chesterfield
2025-01-30[AMDGPU] S_SET_GPR_IDX_ON can be passed an immediate index (#125086)Jon Chesterfield
2025-01-27[AMDGPU][True16][MC] true16 for minimummaximum/max/min/max3/min3 (#124184)Brox Chen
2025-01-22[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (N...Venkata Ramanaiah Nalamothu
2025-01-21[AMDGPU] Fix warningsKazu Hirata
2025-01-22[AMDGPU] Add commute for some VOP3 inst (#121326)Shoreshen
2025-01-11[AMDGPU] Add target hook to isGlobalMemoryObject (#112781)Austin Kerbow
2025-01-07AMDGPU: Fix assert on physreg MUBUF rsrc operand (#120815)Matt Arsenault
2025-01-06[AMDGPU][True16][MC] true16 for v_fma_f16 (#119477)Brox Chen
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