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path: root/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
AgeCommit message (Expand)Author
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus
2025-05-17[llvm] Use llvm::is_sorted (NFC) (#140399)Kazu Hirata
2025-04-27[AMDGPU][True16][CodeGen] update wwm reg sorting check condition (#135053)Brox Chen
2025-04-25Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)Diana Picus
2025-04-23Revert "[AMDGPU] Support block load/store for CSR" (#136846)Diana Picus
2025-04-23[AMDGPU] Support block load/store for CSR (#130013)Diana Picus
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve
2025-02-20[FrameLowering] Use MCRegister instead of Register in CalleeSavedInfo. NFC (#...Craig Topper
2025-01-24[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)Aaditya
2025-01-14[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)Guy David
2024-11-20[AMDGPU] Fix restores in chain functions (#116193)Diana Picus
2024-10-18[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::has...Alex Rønne Petersen
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan
2024-09-26[AMDGPU] Merge the conditions used for deciding CS spills for amdgpu_cs_chain...Christudasan Devadasan
2024-09-24[AMDGPU] Fix handling of DBG_VALUE_LIST while fixing the dead frame indices. ...Pravin Jagtap
2024-09-20[AMDGPU] Use Lo_32 and Hi_32 helpers (NFC) (#109413)Nikita Popov
2024-09-13Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)Diana Picus
2024-09-12Revert "Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)...Diana Picus
2024-09-12Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)" (#108173)Diana Picus
2024-09-10Revert "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108054)Vitaly Buka
2024-09-10[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic (#105822)Diana Picus
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-05-29[AMDGPU] Reserved private memory register during PEI (#93536)Pankaj Dwivedi
2024-05-01[AMDGPU] change order of fp and sp in kernel prologue (#90626)Gang Chen
2024-02-23[AMDGPU][NFC] Have helpers to deal with encoding fields. (#82772)Ivan Kosarev
2024-02-09Revert "[AMDGPU] Compiler should synthesize private buffer resource descripto...Jan Patrick Lehr
2024-02-08[AMDGPU] Compiler should synthesize private buffer resource descriptor from f...alex-t
2024-02-05[AMDGPU] Insert spill codes for the SGPRs used for EXEC copy (#79428)Christudasan Devadasan
2024-01-24[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)Christudasan Devadasan
2024-01-18[AMDGPU] Work around s_getpc_b64 zero extending on GFX12 (#78186)Jay Foad
2023-12-15[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)Mirko Brkušanin
2023-11-14[AMDGPU] Use immediates for stack accesses in chain funcs (#71913)Diana
2023-11-08[AMDGPU] Fix -Wunused-variable in SIFrameLowering.cpp (NFC)Jie Fu
2023-11-08[RegScavenger] Simplify state tracking for backwards scavenging (#71202)Jay Foad
2023-11-08[AMDGPU][PEI] Set up SP for chain functionsDiana Picus
2023-11-08[AMDGPU] Callee saves for amdgpu_cs_chain[_preserve] (#71526)Diana
2023-10-27[AMDGPU] Add pseudo instructions for SGPR spill to VGPR (#69923)Christudasan Devadasan
2023-09-21[AMDGPU] [SIFrameLowering] Use LiveRegUnits instead of LivePhysRegs.Pranav Taneja
2023-09-12[AMDGPU] Add utilities to track number of user SGPRs. NFC.Austin Kerbow
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan
2023-06-29[AMDGPU] Reserve SGPR pair when long branches are presentBrendon Cahoon
2023-06-15[AMDGPU] Remove return VGPRs from callee save listCarl Ritson
2023-05-24[AMDGPU] Check if register is non-null before calling isSubRegisterEq (NFCI)Sergei Barannikov
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